Creating a Vivado SDK/Vitis project

This guide will cover creating and managing projects using Xilinx SDK (2019.1) and Vitis (2020.1+) for Red Pitaya embedded software development.

Note

Coming soon.

This section is currently under development and will include comprehensive guidance on:

• Setting up SDK/Vitis workspace

• Creating embedded software projects

• Debugging applications on Red Pitaya

• FSBL (First Stage Boot Loader) customization

• Integration with FPGA designs

See also

Currently Available Documentation:

For FPGA development without SDK/Vitis, see:

• Creating an FPGA project in Vivado - Creating FPGA projects in Vivado

• Modifying the FPGA project - Modifying existing FPGA designs

• Installation of Xilinx SDK 2019.1 - SDK installation guide

• FPGA Reprogramming Guide - Loading FPGA bitstreams