4.3. FPGA section

This section describes how to build and modify the FPGA design for Red Pitaya boards. It is intended for users who want to create their own FPGA projects or modify existing ones using Xilinx Vivado.

Prerequisites: Basic knowledge of digital logic design, Verilog/VHDL, and familiarity with Xilinx Vivado development environment. Experience with Linux command line is helpful.


4.3.2. Typical FPGA Development Workflow

1. Environment Setup

  • Install Xilinx Vivado 2020.1 (required for building FPGA images)

  • Install Xilinx SDK 2019.1 (required if modifying ARM software)

  • Clone the Red Pitaya FPGA repository

  • Familiarize yourself with the repository structure

2. Choose Your Starting Point

  • Modify existing project: Start with a standard project (v0.94, streaming, axi4lite) and customize

  • Create new project: Use an existing project as template, modify functionality

  • Add custom IP: Integrate your own Verilog/VHDL modules into existing design

3. Development Cycle

  1. Design: Modify RTL code or block diagram in Vivado

  2. Simulate: Run behavioral simulation to verify logic and catch errors early (Essential step - saves hours of debugging)

  3. Synthesize: Run synthesis to check for errors and resource usage

  4. Implement: Place and route the design

  5. Generate bitstream: Create the FPGA binary file (.bit)

  6. Test: Load bitstream to Red Pitaya and verify functionality

Note

Why simulation is critical: Simulating your design catches logical errors, timing issues, and functionality problems in minutes, whereas deploying to hardware and debugging can take hours. Always simulate before synthesis, especially when learning FPGA development.

4. Integration

  • Create or modify device tree if adding new peripherals

  • Update software drivers/APIs to interface with new FPGA functionality

  • Document register maps and usage

5. Deployment

  • Copy bitstream to Red Pitaya

  • Load at runtime using the overlay system

  • Configure automatic loading at boot (optional)


4.3.3. What’s in each section

  • Getting Started - Vivado/SDK installation, project creation, simulation setup, FPGA reprogramming basics

  • FPGA Tutorials - Step-by-step guides for common FPGA development tasks (coming soon)

  • FPGA Projects - Available projects (v0.94, streaming, mercury, etc.), repository structure, project descriptions

  • Registers - Memory-mapped register addresses and descriptions by OS version

  • Advanced Topics - Boot configuration, JTAG programming, device trees, signal mapping