Phase locked loop
Functionality overview
Phase-locked loop (PLL) commands control the clock synchronization circuitry exclusive to SIGNALlab 250-12. The PLL allows precise frequency and phase locking to external reference clock signals for applications requiring tight timing synchronization.
Important notes
These commands only work on SIGNALlab 250-12.
The external reference clock should be connected to the 10 MHz SMA connector at the back of the board.
Code examples
[To be added - examples specific to PLL usage]
Parameters and command table
Parameter options:
<enable> = {OFF, ON}<status> = {true, false}
SCPI |
API, Jupyter |
DESCRIPTION |
ECOSYSTEM |
|---|---|---|---|
RP:PLL:ENable <enable>Examples:
RP:PLL:ENable ON |
C++:
rp_SetPllControlEnable(bool enable)Python:
rp_SetPllControlEnable(<enable>) |
Enables/disables PLL control (SIGNALlab 250-12 only).
Enables synchronisation with the 10 MHz reference clock connected to the
SMA connector at the back.
|
2.04-35 and up |
RP:PLL:ENable? > <enable>Examples:
RP:PLL:ENable? > ON |
C++:
rp_GetPllControlEnable(bool *enable)Python:
rp_GetPllControlEnable() |
Get the state of the PLL enable setting (SIGNALlab 250-12 only). |
2.04-35 and up |
RP:PLL:STATE? > <status>Examples:
RP:PLL:STATE? > 1 |
C++:
rp_GetPllControlLocked(bool *status)Python:
rp_GetPllControlLocked() |
Get the status of the PLL synchronisation with the reference clock
1 - Unit is synced with the reference clock0 - Unit is not synced with the reference clock(SIGNALlab 250-12 only).
|
2.04-35 and up |