FPGA projects

This section contains information about various FPGA projects available for Red Pitaya. Each project is designed to demonstrate different functionalities and capabilities of the FPGA hardware.

Related Documentation:

• FPGA Register Maps - Detailed register documentation for each project

• FPGA Development - General FPGA development guide

FPGA repository

Before we jump to the projects, let’s take a look at the FPGA GitHub repository structure.

The repository contains multiple FPGA projects, with either generic functionality or specific functionality related to a particular application.

• Code common to all projects, which mostly contains reusable modules, is directly in the top directory.

• Project-specific code is located inside the prj/<project_name>/ directories.

Path	Contents
archive/	Archive of old FPGA bit files compressed in .xz format
brd/	Board files (Vivado System-Level Design Entry)
doc/	Documentation (block diagrams, address space, …)
dts/	Device tree source include files
ip/	Third party IP, for now, Zynq block diagrams
prj/name	Project name specific code
rtl/	Verilog (SystemVerilog) Register-Transfer Level
sdc/	Synopsys Design Constraints contains Xilinx design constraints
sim/	Simulation scripts
tbn/	Verilog (SystemVerilog) test bench
Makefile	Main Makefile, used to run FPGA-related tools
*.tcl	TCL scripts to be run inside FPGA tools
*.rst	ReStructuredText files for documentation

FPGA projects

All existing projects have either generic functionality or specific functionality related to a particular application as described in the “Application” column.

We recommend using the 0.94 as the default project.

Project name	Description	Application	Status
0.94	The core project that contains most of the available functionality. Also the core for all future development. Main improvements over 0.93: 1. The CDC (clock domain crossing) code on the custom CPU bus was removed. Instead, the CDC for the GP0 port, which was already available in the PS, was used. This improves speed and reliability, while reducing RTL complexity. 2. A bug in the generator that caused a value increment was fixed; this should improve the generated frequencies near the half- sampling rate. 3. The XADC custom RTL wrapper was replaced with the Xilinx AXI XADC. This enables the use of the Linux driver with IIO streaming support.	Oscilloscope Signal generator Arbitrary waveform generator Spectrum analyzer Bode analyzer Impedance analyzer LCR meter JupyterLab Register map: v0.94	Active
stream_app	1. Streaming of ADC and DAC data to and from DDR3 memory buffers. 2. Streaming of GPIO inputs and outputs to/from DDR3 memory buffers.	Data stream control (streaming application) Register maps: In Dev	Active
logic	The DMA is used to transfer data to the main DDR3 RAM. The ADC and DAC code is unfinished.	Logic analyzer	Active
0.93	The original Red Pitaya FPGA release with all original bugs. For deprecated application backward compatibility only.		Legacy
classic	1. Most of the code is rewritten in SystemVerilog. 2. The GPIO and LED registers were removed from the housekeeping section; instead, the GPIO controller inside the PL is used. This allows Linux kernel features to be used for GPIO (IRQ, SPI, I2C and 1-Wire) and LEDs (triggers).		Legacy
axi4lite	This image is intended for testing various AXI4 bus implementations. It contains a Vivado Integrated Logic Analyser (ILA) for observing and reviewing the performance of the bus implementation.		Legacy
tft	The TFT FPGA image supports connection to TFT displays, with instructions available here. Compatible with 0.97 and 0.98 OS versions.		Legacy
mercury	The old image used by Jupyter Notebook application. Replaced by Python API commands in the latest OS versions.	Jupyter Notebook	Legacy

In-depth project descriptions

• FPGA project v0.94
• FPGA stream app project
• FPGA logic project

Board compatibility

Not all projects are compatible with all Red Pitaya boards. The table below shows the compatibility of each project with the different board versions.

The following table shows which projects are available on which boards.

Build name	Build Project Flag	STEMlab 125-10 STEMlab 125-14 STEMlab 125-14-Z7020	SIGNALlab 250-12	SDRlab 122-16	STEMlab 125-14 4-Input
0.94	v0.94	X		X	X
0.94_250	v0.94_250		X
stream_app	stream_app	X		X
stream_app_250	stream_app_250		X
logic	logic	X
logic_250	logic_250		X
tft	tft	X
axi4lite	axi4lite	X
classic	classic	X
mercury	mercury	X

Build name	Build Project Flag	STEMlab 125-10 STEMlab 125-14 STEMlab 125-14 Z7020	STEMlab 125-14 Gen 2 STEMlab 125-14 PRO Gen 2 STEMlab 125-14 PRO Z7020 Gen 2 STEMlab 125-14 TI STEMlab 65-16 TI SDRlab 122-16 STEMlab 125-14 4-Input	SIGNALlab 250-12
Active
0.94	v0.94	X	X
0.94_250	v0.94_250			X
stream_app	stream_app	X	X
stream_app_250	stream_app_250			X
logic	logic	X	X
logic_250	logic_250			X
Legacy
tft	tft	X
axi4lite	axi4lite	X
classic	classic	X
mercury	mercury	X

Note

Legacy projects are not actively maintained and may not be compatible with the latest hardware revisions or software versions. It is recommended to use active projects for new developments.