FPGA projects

This section contains information about various FPGA projects available for Red Pitaya. Each project is designed to demonstrate different functionalities and capabilities of the FPGA hardware.

Related Documentation:

• FPGA Register Maps - Detailed register documentation for each project

• FPGA Development - General FPGA development guide

• Creating a Custom Project from Scratch - Constraint and model/configuration file selection for manual project creation

FPGA repository

Before we jump to the projects, let’s take a look at the FPGA GitHub repository structure.

The repository contains multiple FPGA projects, with either generic functionality or specific functionality related to a particular application.

• Code common to all projects, which mostly contains reusable modules, is directly in the top directory.

• Project-specific code is located inside the prj/<project_name>/ directories.

Path	Contents
archive/	Archive of old FPGA bit files compressed in .xz format
brd/	Board files (Vivado System-Level Design Entry)
doc/	Documentation (block diagrams, address space, …)
dts/	Device tree source include files
ip/	Third party IP, for now, Zynq block diagrams
prj/name	Project name specific code
rtl/	Verilog (SystemVerilog) Register-Transfer Level
sdc/	Synopsys Design Constraints contains Xilinx design constraints
sim/	Simulation scripts
tbn/	Verilog (SystemVerilog) test bench
Makefile	Main Makefile, used to run FPGA-related tools
*.tcl	TCL scripts to be run inside FPGA tools
*.rst	ReStructuredText files for documentation

FPGA projects

All existing projects have either generic functionality or specific functionality related to a particular application as described in the “Application” column.

We recommend using the 0.94 as the default project.

Project name	Description	Application	Status
0.94	Default and most feature-complete Red Pitaya FPGA image. Used as the baseline for current application support and most custom forks. In the 2025.1 flow it remains the recommended starting point.	Oscilloscope Signal generator Spectrum analyzer Bode analyzer Impedance analyzer LCR meter JupyterLab Register map: v0.94	Active (default)
stream_app	High-throughput streaming project. Supports ADC/DAC/GPIO transfer between PL and DDR memory, and host-to-board streaming workflows. Includes board-specific variants (for example 4-input and 250-12).	Data streaming Streaming server / API flows Register maps: In Dev	Active
logic	Logic-analyzer oriented project with DMA-based capture to DDR. Focuses on digital acquisition and protocol analysis workflows.	Logic analyzer	Active
barebones	Linux platform base with shared PS configuration used across projects. Builds the full Linux device tree; other projects typically provide overlays only. Keeps application layer intentionally minimal/empty.	Foundation for Linux system	Active
pyrpl	Third-party oriented image for PyRPL workflows, including lock-in, IQ, filter, and feedback-control related DSP blocks.	PyRPL / control loops (advanced DSP/control)	Community
fsbl	Build-support project for FSBL and U-Boot artifacts (XSA/FSBL flow). Similar to barebones but with fewer enabled peripherals/settings, because U-Boot does not require the full Linux platform scope.	Boot and platform artifacts	Build support
Examples	Collection of standalone educational Vivado examples (for example LED/GPIO/VGA exercises). Useful for training and quick experiments.	Learning and quick demos	Legacy

The table above reflects projects currently present in prj/ on the master branch of the FPGA repository. Older projects from previous releases may still be available in historical tags.

Legacy projects

These projects are no longer in the FPGA repository and are not actively maintained. They may be incompatible with the latest hardware revisions or software versions. Use them only for reference or if you are maintaining older systems.

Project name	Description	Application	Status
0.93	The original Red Pitaya FPGA release with all original bugs. For deprecated application backward compatibility only.		Legacy
classic	1. Most of the code is rewritten in SystemVerilog. 2. The GPIO and LED registers were removed from the housekeeping section; instead, the GPIO controller inside the PL is used. This allows Linux kernel features to be used for GPIO (IRQ, SPI, I2C and 1-Wire) and LEDs (triggers).		Legacy
axi4lite	This image is intended for testing various AXI4 bus implementations. It contains a Vivado Integrated Logic Analyser (ILA) for observing and reviewing the performance of the bus implementation.		Legacy
tft	The TFT FPGA image supports connection to TFT displays, with instructions available here. Compatible with 0.97 and 0.98 OS versions.		Legacy
mercury	The old image used by Jupyter Notebook application. Replaced by Python API commands in the latest OS versions.	Jupyter Notebook	Legacy

In-depth project descriptions

The following pages cover active projects in the current repository layout. PyRPL and Examples are intentionally not covered here.

• FPGA project v0.94
• FPGA stream app project
• FPGA logic project
• FPGA barebones project
• FPGA fsbl project

Board compatibility

Not all projects are compatible with all Red Pitaya boards. The table below shows the compatibility of each project with the different board versions.

The following table shows which projects are available on which boards.

Build name	Build Project Flag	STEMlab 125-10 STEMlab 125-14 STEMlab 125-14-Z7020	SIGNALlab 250-12	SDRlab 122-16	STEMlab 125-14 4-Input	STEMlab 125-14 Gen 2 STEMlab 125-14 PRO Gen 2 STEMlab 125-14 PRO Z7020 Gen 2 STEMlab 125-14 TI STEMlab 65-16 TI
Active projects
0.94	v0.94	X		X	X	X
0.94_250	v0.94_250		X
stream_app	stream_app	X		X	X	X
stream_app_250	stream_app_250		X
logic	logic	X			X	X
logic_250	logic_250		X
barebones	barebones	X	X	X	X	X
fsbl	fsbl	X	X	X	X	X
Legacy projects
tft	tft	X
axi4lite	axi4lite	X
classic	classic	X
mercury	mercury	X

Model	Build Model flag
STEMlab 125-14 PRO Gen 2 STEMlab 125-14 Gen 2 STEMlab 125-14 STEMlab 125-10	MODEL=Z10
STEMlab 125-14 Z7020	MODEL=Z20_14
SDRlab 122-16	MODEL=Z20
SIGNALlab 250-12	MODEL=Z20_250
STEMlab 125-14 4-Input	MODEL=Z20_4
STEMlab 125-14 PRO Z7020 Gen 2	MODEL=Z20_G2
STEMlab 125-14 TI STEMlab 65-16 TI	MODEL=Z20_ll

Note

Legacy projects are not actively maintained and may not be compatible with the latest hardware revisions or software versions. It is recommended to use active projects for new developments.