FPGA Register Map - v0.94

FPGA Project: v0.94

Compatible Boards:

• STEMlab 125-14 Gen 2

• STEMlab 125-14 PRO Gen 2

• STEMlab 125-14 PRO Z7020 Gen 2

• STEMlab 125-14 TI

• STEMlab 65-16 TI

• STEMlab 125-14

• STEMlab 125-14 Z7020

• STEMlab 125-14 4-Input

• SDRlab 122-16

• STEMlab 125-10

Compatible applications:

• Oscilloscope

• Signal Generator

• Arbitrary Waveform Generator

• Spectrum Analyzer

• Bode Analyzer

• Impedance Analyzer

• LCR Meter

• JupyterLab

This document describes the FPGA register map for the v0.94 project, which is the recommended default project for most Red Pitaya applications. It contains the core functionality and serves as the base for all future development.

Red Pitaya HDL design has multiple functions, which are configured by registers. It also uses memory locations to store capture data and generate output signals. All of these are described in this document. The memory locations are written in a way that is seen by the software.

The table describes address space partitioning implemented on FPGA via the AXI GP0 interface. All registers have offsets aligned to 4 bytes and are 32-bit wide. Granularity is 32-bit, meaning that the minimum transfer size is 4 bytes. The organization is little-endian. The memory block is divided into 8 parts. Each part is occupied by an individual IP core. The address space of individual applications is described in the subsection below. The size of each IP core address space is 4 MByte.

Memory Map Overview

	Start	End	Module Name
CS[0]	0x40000000	0x400FFFFF	Housekeeping
CS[1]	0x40100000	0x401FFFFF	Oscilloscope (CH A/B)
CS[2]	0x40200000	0x402FFFFF	Arbitrary signal generator (ASG) STEMlab 125-14 4-Input: Oscilloscope CH C/D
CS[3]	0x40300000	0x403FFFFF	PID controller
CS[4]	0x40400000	0x404FFFFF	Analog mixed signals (AMS)
CS[5]	0x40500000	0x405FFFFF	Daisy chain
CS[6]	0x40600000	0x406FFFFF	FREE STEMlab 125-14 PRO Z7020 Gen 2: E3 connector serial lines test
CS[7]	0x40700000	0x407FFFFF	Power test

CS[0] - Housekeeping (0x40000000-0x400FFFFF)

The Housekeeping module provides system identification, GPIO control, and board-specific features.

Quick Reference

Common Registers (All Boards)

Offset	Register	R/W
0x0	Design ID	R
0x4-0x8	Device DNA (unique identifier)	R
0xC	Digital loopback	R/W
0x10-0x24	GPIO direction and data (P/N)	R/W
0x30	LED control	R/W
0x34	CAN bus enable	R/W
0x100	FPGA ready status	R
0x104	ADC clock frequency meter	R
0x1000	External trigger override	R/W

Board-Specific Registers

TI boards:

Offset	Register	R/W
0x40	IDELAY control	R/W
0x50-0x58	ADC SPI interface	R/W

125-14 4-Input board:

Offset	Register	R/W
0x40	PLL control	R/W
0x44	IDELAY reset	R/W
0x48-0x54	IDELAY CH A/B/C/D	R/W

Common Registers - All Boards

System Identification

Offset	Description	Bits	R/W
0x0	Design ID
	Reserved	31:4	R
	Design ID: 0 = prototype 1 = release	3:0	R
0x4	DNA part 1
	Device unique identifier [31:0]	31:0	R
0x8	DNA part 2
	Reserved	31:25	R
	Device unique identifier [56:32]	24:0	R

GPIO Control

Offset	Description	Bits	R/W
0x10	Expansion connector direction P
	Reserved	31:8	R
	Direction for P lines: 1 = output 0 = input	7:0	R/W
0x14	Expansion connector direction N
	Reserved	31:8	R
	Direction for N lines: 1 = output 0 = input	7:0	R/W
0x18	Expansion connector output P
	Reserved	31:8	R
	P pins output value	7:0	R/W
0x1C	Expansion connector output N
	Reserved	31:8	R
	N pins output value	7:0	R/W
0x20	Expansion connector input P
	Reserved	31:8	R
	P pins input value	7:0	R
0x24	Expansion connector input N
	Reserved	31:8	R
	N pins input value	7:0	R

System Control

Offset	Description	Bits	R/W
0xC	Digital Loopback
	Reserved	31:1	R
	Enable digital loopback: 1 = enabled 0 = disabled	0	R/W
0x30	LED control
	Reserved	31:8	R
	LED state: 1 = on 0 = off	7:0	R/W
0x34	CAN pins enable
	Reserved	31:1	R
	Enable CAN0 and CAN1 pins: CAN0_rx: GPIO_P 7 CAN0_tx: GPIO_N 7 CAN1_rx: GPIO_P 6 CAN1_tx: GPIO_N 6	0	R/W
0x100	FPGA ready
	Reserved	31:1	R
	Programmable logic is out of reset 1 = ready 0 = not ready	0	R
0x104	ADC clock frequency meter
	Approximate frequency of ADC clock (Hz)	31:0	R

Trigger Control

Offset	Description	Bits	R/W
0x1000	External trigger override
	Reserved	31:3	R
	Trigger output selector: 1 = DAC trigger 0 = ADC trigger	2	R/W
	Override GPIO_N 0 to output ADC or DAC trigger	1	R/W
	Enable external trigger through daisy chain: 1 = enable 0 = disable	0	R/W

Board-Specific Registers

TI boards Only

IDELAY Control

Offset	Description	Bits	R/W
0x40	IDELAY control
	Reserved	31:25	R
	IDELAY value in taps (pair ADB1)	24:20	R/W
	IDELAY value in taps (pair ADB0)	19:15	R/W
	IDELAY value in taps (pair ADA1)	14:10	R/W
	IDELAY value in taps (pair ADA0)	9:5	R/W
	IDELAY value in taps (pair ADFCLK)	4:0	R/W

ADC SPI Interface

Offset	Description	Bits	R/W
0x50	ADC SPI control
	Reserved	31:16	R
	Control word	15:0	R/W
0x54	ADC SPI write
	Reserved	31:16	R
	Write data to ADC (only 8 LSB bits valid)	15:0	R/W
0x58	ADC SPI read
	Reserved	31:17	R
	Transfer busy 1 = busy 0 = ready to transmit	16	R
	Reserved	15:8	R
	Read data (only 8 LSB bits valid)	7:0	R

125-14 4-Input Only

PLL and Clock Control

Offset	Description	Bits	R/W
0x40	PLL control
	Reserved	31:9	R
	PLL locked status: 1 = locked 0 = not locked	8	R
	Reserved	7:5	R
	Reference clock detected: 1 = detected 0 = no external clock detected	4	R
	Reserved	3:1	R
	Enable PLL: 1 = enabled 0 = disabled	0	R/W

IDELAY Configuration

Note

IDELAY registers for channels A/B/C/D share the same structure. Each channel has:

• inc/dec bits [14:8] - Increment/decrement delay taps

• enable bits [6:0] - Enable delay adjustment

• stage bits [4:0] - Current delay stage (read-only)

Offset	Description	Bits	R/W
0x44	IDELAY reset
	Reserved	31:15	R
	CH B[6:0] idelay reset	14:8	R/W
	Reserved	7	R
	CH A[6:0] idelay reset	6:0	R/W
0x48	IDELAY CH A
	Reserved	31:15	R
	CH A[6:0] inc/dec	14:8	W
	Reserved	7	R
	CH A[6:0] idelay enable	6:0	W
	CH A[0] current idelay tap value	4:0	R
0x4C	IDELAY CH B (same structure as CH A)
0x50	IDELAY CH C (same structure as CH A)
0x54	IDELAY CH D (same structure as CH A)

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CS[1] - Oscilloscope (0x40100000-0x401FFFFF)

The Oscilloscope module handles ADC data acquisition, triggering, and buffering.

Note

STEMlab 125-14 4-Input: Register writes are duplicated for channels A/B and C/D. Output registers (ASG) are replaced with mirrored input registers for channels C/D (IN3/IN4). For complete CH C/D registers, see CS[2] Oscilloscope CH C/D.

Quick Reference

Offset	Register	R/W
0x0	Configuration & status	R/W
0x4	Trigger source selector	R/W
0x8-0xC	CH A/B threshold	R/W
0x10	Delay after trigger (CH A)	R/W
0x14	Data decimation (CH A)	R/W
0x18-0x1C	Write pointers (current/trigger)	R
0x20-0x24	CH A/B hysteresis	R/W
0x28	Signal average enable	R/W
0x2C	PreTrigger counter	R
0x30-0x4C	CH A/B Equalization filters (AA/BB/KK/PP)	R/W
0x50-0x64	CH A AXI DMA control	R/W
0x70-0x84	CH B AXI DMA control	R/W
0x88	AXI state registers	R
0x90	Trigger debouncer time	R/W
0x94	Trigger protection clear	W
0x98	Reconstruction filter bypass	R/W
0xA0	Accumulator data sequence length	R
0xA4-0xA8	Accumulator offset correction (CH A/B)	R/W
0x110	Delay after trigger (CH B)	R/W
0x114	Data decimation (CH B)	R/W
0x118-0x11C	CH B write pointers (current/trigger)	R
0x120-0x12C	Calibration (TI and 122-16 models)	R/W
0x200-0x20C	Calibration (other models)	R/W
0x10000-0x1FFFC	CH A memory buffer (16k samples)	R
0x20000-0x2FFFC	CH B memory buffer (16k samples)	R

Trigger Sources

The trigger source register (0x4) accepts the following values:

Value	Trigger Source
0	Disabled
1	Trigger immediately
2	CH A threshold positive edge
3	CH A threshold negative edge
4	CH B threshold positive edge
5	CH B threshold negative edge
6	External trigger positive edge (DIO0_P pin)
7	External trigger negative edge
8	AWG application positive edge
9	AWG application negative edge
10	CH C threshold positive edge (4-Input only)
11	CH C threshold negative edge (4-Input only)
12	CH D threshold positive edge (4-Input only)
13	CH D threshold negative edge (4-Input only)
18	CH A threshold any edge
20	CH B threshold any edge
22	External trigger any edge
24	AWG any edge
26	CH C threshold any edge (4-Input only)
28	CH D threshold any edge (4-Input only)

Configuration and Control

Offset	Description	Bits	R/W
0x0	Configuration
	Channel 1 (CH A)
	Reserved	7:6	R
	Enable split trigger mode	5	R/W
	Acquisition delay complete (all data written to buffer)	4	R
	Trigger remains armed after acquisition delay completes	3	W
	Trigger has arrived (stays 1 until next arm or reset)	2	R
	Reset write state machine	1	W
	Start writing data into memory (ARM trigger)	0	W
	Channel 2 (CH B)
	Reserved	15:14	R
	Enable split trigger mode	13	R/W
	Acquisition delay complete (all data written to buffer)	12	R
	Trigger remains armed after acquisition delay completes	11	W
	Trigger has arrived (stays 1 until next arm or reset)	10	R
	Reset write state machine	9	W
	Start writing data into memory (ARM trigger)	8	W
	Channel 3 (CH C) — 4-Input only
	Reserved	23:22	R
	Enable split trigger mode	21	R/W
	Acquisition delay complete (all data written to buffer)	20	R
	Trigger remains armed after acquisition delay completes	19	W
	Trigger has arrived (stays 1 until next arm or reset)	18	R
	Reset write state machine	17	W
	Start writing data into memory (ARM trigger)	16	W
	Channel 4 (CH D) — 4-Input only
	Reserved	31:30	R
	Enable split trigger mode	29	R/W
	Acquisition delay complete (all data written to buffer)	28	R
	Trigger remains armed after acquisition delay completes	27	W
	Trigger has arrived (stays 1 until next arm or reset)	26	R
	Reset write state machine	25	W
	Start writing data into memory (ARM trigger)	24	W
0x4	Trigger source - See trigger source table above
	Channel 1 (CH A)
	Reserved	7:6	R
	Trigger lock status (1 = locked/armed, 0 = waiting/idle)	5	R
	Trigger source selector (when trigger delay ends → 0)	4:0	R/W
	Channel 2 (CH B)
	Reserved	15:14	R
	Trigger lock status (1 = locked/armed, 0 = waiting/idle)	13	R
	Trigger source selector (when trigger delay ends → 0)	12:8	R/W
	Channel 3 (CH C) — 4-Input only
	Reserved	23:22	R
	Trigger lock status (1 = locked/armed, 0 = waiting/idle)	21	R
	Trigger source selector (when trigger delay ends → 0)	20:16	R/W
	Channel 4 (CH D) — 4-Input only
	Reserved	31:30	R
	Trigger lock status (1 = locked/armed, 0 = waiting/idle)	29	R
	Trigger source selector (when trigger delay ends → 0)	28:24	R/W

Threshold and Timing

Offset	Description	Bits	R/W
0x8	CH A threshold
	Reserved	31:14	R
	Trigger when ADC value crosses this threshold	13:0	R/W
0xC	CH B threshold
	Reserved	31:14	R
	Trigger when ADC value crosses this threshold	13:0	R/W
0x10	Delay after trigger
	Number of decimated samples to capture after trigger	31:0	R/W
0x14	Data decimation
	Reserved	31:17	R
	Decimation factor: 1, 2, 4, 8: Supported for values < 16 ≥16: Averaging of any number supported (max 65535)	16:0	R/W
0x20	CH A hysteresis
	Reserved	31:14	R
	Threshold hysteresis - value must be outside to re-trigger	13:0	R/W
0x24	CH B hysteresis
	Reserved	31:14	R
	Threshold hysteresis - value must be outside to re-trigger	13:0	R/W

Tip

Hysteresis usage: Set hysteresis to prevent trigger noise. The signal must move outside the hysteresis band before the trigger can fire again.

Write Pointers and Configuration

Offset	Description	Bits	R/W
0x18	Write pointer - current
	Reserved	31:14	R
	Current write pointer	13:0	R
0x1C	Write pointer - trigger
	Reserved	31:14	R
	Write pointer at time when trigger arrived	13:0	R
0x28	Signal average enable
	Channel 1
	Reserved	7:2	R
	Enables 16-bit mode. Data is expanded to 16 bits.	1	R/W
	Enable signal average at decimation	0	R/W
	Channel 2
	Reserved	15:10	R
	Enables 16-bit mode. Data is expanded to 16 bits.	9	R/W
	Enable signal average at decimation	8	R/W
	Channel 3 — 4-Input only
	Reserved	23:18	R
	Enables 16-bit mode. Data is expanded to 16 bits.	17	R/W
	Enable signal average at decimation	16	R/W
	Channel 4 — 4-Input only
	Reserved	31:26	R
	Enables 16-bit mode. Data is expanded to 16 bits.	25	R/W
	Enable signal average at decimation	24	R/W
0x2C	PreTrigger Counter
	Unsigned counter holding the number of samples captured between acquisition start and trigger. Stops incrementing at 0xffffffff (no overflow).	31:0	R

Equalization Filters

Offset	Description	Bits	R/W
0x30	CH A Equalization filter AA
	Reserved	31:18	R
	AA Coefficient	17:0	R/W
0x34	CH A Equalization filter BB
	Reserved	31:25	R
	BB Coefficient	24:0	R/W
0x38	CH A Equalization filter KK
	Reserved	31:25	R
	KK Coefficient	24:0	R/W
0x3C	CH A Equalization filter PP
	Reserved	31:25	R
	PP Coefficient	24:0	R/W
0x40	CH B Equalization filter AA
	Reserved	31:18	R
	AA Coefficient	17:0	R/W
0x44	CH B Equalization filter BB
	Reserved	31:25	R
	BB Coefficient	24:0	R/W
0x48	CH B Equalization filter KK
	Reserved	31:25	R
	KK Coefficient	24:0	R/W
0x4C	CH B Equalization filter PP
	Reserved	31:25	R
	PP Coefficient	24:0	R/W

AXI DMA Control

Offset	Description	Bits	R/W
0x50	CH A AXI lower address
	Starting write address for DMA buffer	31:0	R/W
0x54	CH A AXI upper address
	Upper address limit (wraps to lower address)	31:0	R/W
0x58	CH A AXI delay after trigger
	Number of decimated samples to write after trigger	31:0	R/W
0x5C	CH A AXI enable master
	Reserved	31:1	R
	Enable AXI master for DMA transfers	0	R/W
0x60	CH A AXI write pointer - trigger
	Write pointer at time when trigger arrived	31:0	R
0x64	CH A AXI write pointer - current
	Current write pointer	31:0	R
0x70	CH B AXI lower address
	Starting write address for DMA buffer	31:0	R/W
0x74	CH B AXI upper address
	Upper address limit (wraps to lower address)	31:0	R/W
0x78	CH B AXI delay after trigger
	Number of decimated samples to write after trigger	31:0	R/W
0x7C	CH B AXI enable master
	Reserved	31:1	R
	Enable AXI master for DMA transfers	0	R/W
0x80	CH B AXI write pointer - trigger
	Write pointer at time when trigger arrived	31:0	R
0x84	CH B AXI write pointer - current
	Current write pointer	31:0	R
0x88	AXI state registers
	Reserved	31:21	R
	CH B AXI - Acquisition delay complete (all data written to buffer)	20	R
	CH B AXI - Trigger remains armed after acquisition delay completes	19	R
	CH B AXI - Trigger has arrived (stays 1 until next arm or reset)	18	R
	Reserved	17	R
	CH A AXI - Trigger armed	16	R
	Reserved	15:5	R
	CH A AXI - Acquisition delay complete (all data written to buffer)	4	R
	CH A AXI - Trigger remains armed after acquisition delay completes	3	R
	CH A AXI - Trigger has arrived (stays 1 until next arm or reset)	2	R
	Reserved	1	R
	CH A AXI - Trigger armed	0	R

Additional Configuration

Offset	Description	Bits	R/W
0x90	Trigger debouncer time
	Number of ADC clock periods trigger is disabled after activation. Reset value is decimal 62500, equivalent to 0.5 ms.	19:0	R/W
0x94	Trigger protection clear
	Channel 1 (CH A)
	Reserved	7:1	R
	Clear trigger protection mechanism	0	W
	Channel 2 (CH B)
	Reserved	15:9	R
	Clear trigger protection mechanism	8	W
	Channel 3 (CH C) — 4-Input only
	Reserved	23:17	R
	Clear trigger protection mechanism	16	W
	Channel 4 (CH D) — 4-Input only
	Reserved	31:25	R
	Clear trigger protection mechanism	24	W
0x98	Reconstruction filter bypass
	Reserved	31:2	R
	Filter bypass CH B	1	R/W
	Filter bypass CH A	0	R/W

Note

For 4-channel boards (STEMlab 125-14 4-Input), the value of this register must be written to both CS[1] (0x40100090) and CS[2] (0x40200090) for proper debouncer operation on all channels.

Interrupt Control (IRQ)

Offset	Description	Bits	R/W
0xAC	IRQ Mask
	Reserved	31:2	R
	Buffer full interrupt enable	1	R/W
	Trigger interrupt enable	0	R/W
0xB0	IRQ Status / Clear
	Read: latched status; Write 1 to clear the bit
	Reserved	31:2	R
	Buffer full interrupt pending	1	R/W
	Trigger interrupt pending	0	R/W
0xB4	Split IRQ Mask (independent mode only)
	Reserve/padding	31:8	R
	Buffer full enable CH4	7	R/W
	Buffer full enable CH3	6	R/W
	Buffer full enable CH2	5	R/W
	Buffer full enable CH1	4	R/W
	Trigger enable CH4	3	R/W
	Trigger enable CH3	2	R/W
	Trigger enable CH2	1	R/W
	Trigger enable CH1	0	R/W
0xB8	Split IRQ Status / Clear
	Read: per-channel latched status; Write 1 to clear
	Reserve/padding	31:8	R
	Buffer full pending CH4	7	R/W
	Buffer full pending CH3	6	R/W
	Buffer full pending CH2	5	R/W
	Buffer full pending CH1	4	R/W
	Trigger pending CH4	3	R/W
	Trigger pending CH3	2	R/W
	Trigger pending CH2	1	R/W
	Trigger pending CH1	0	R/W

Channel B Specific Registers

Offset	Description	Bits	R/W
0x110	Delay after trigger CHB
	Number of decimated samples to write after trigger	31:0	R/W
0x114	Data decimation CH B
	Reserved	31:17	R
	Decimation factor: 1, 2, 4, 8: Supported for values < 16 ≥16: Averaging of any number supported (max 65535)	16:0	R/W
0x118	Write pointer - current CH B
	Reserved	31:14	R
	Current write pointer	13:0	R
0x11C	Write pointer - trigger CH B
	Reserved	31:14	R
	Write pointer at time when trigger arrived	13:0	R
0x12C	PreTrigger Counter CH B (other models)
	Unsigned counter holding the number of samples captured between acquisition start and trigger. Stops incrementing at 0xffffffff (no overflow)	31:0	R

Calibration Registers

Offset	Description	Bits	R/W
0x200	CH A calibration offset (other models)
	Reserved	31:16	R
	Calibration offset (16 bit signed)	15:0	R/W
0x204	CH A calibration gain (other models)
	Reserved	31:16	R
	Calibration gain (16 bit signed)	15:0	R/W
0x208	CH B calibration offset (other models)
	Reserved	31:16	R
	Calibration offset (16 bit signed)	15:0	R/W
0x20C	CH B calibration gain (other models)
	Reserved	31:16	R
	Calibration gain (16 bit signed)	15:0	R/W

Timestamp Registers

Offset	Description	Bits	R/W
0x220	Global Timestamp Counter LO
	Lower 32 bits of the global 64-bit timer. IMPORTANT: Reading this register latches (snapshots) the full 64-bit counter value into a temporary buffer. Always read LO first.
	Global timestamp counter bits [31:0]	31:0	R
0x224	Global Timestamp Counter HI
	Upper 32 bits of the global 64-bit timer. Returns the upper 32 bits of the value latched when LO was read.
	Global timestamp counter bits [63:32]	31:0	R
0x228	CH1 Trigger Timestamp LO
	Lower 32 bits of the timestamp captured at the last CH1 trigger event.
	CH1 trigger timestamp bits [31:0]	31:0	R
0x22C	CH1 Trigger Timestamp HI
	Upper 32 bits of the timestamp captured at the last CH1 trigger event.
	CH1 trigger timestamp bits [63:32]	31:0	R
0x230	CH2 Trigger Timestamp LO
	Lower 32 bits of the timestamp captured at the last CH2 trigger event.
	CH2 trigger timestamp bits [31:0]	31:0	R
0x234	CH2 Trigger Timestamp HI
	Upper 32 bits of the timestamp captured at the last CH2 trigger event.
	CH2 trigger timestamp bits [63:32]	31:0	R

Note

For 4-channel boards (STEMlab 125-14 4-Input), the global counter registers (0x220–0x224) must be written to both CS[1] (0x40100220) and CS[2] (0x40200220) for timestamp synchronization between channel pairs A/B and C/D.

Memory Data Buffers

Offset	Description	Bits	R/W
0x10000 to 0x1FFFC	Memory data (16k samples)
	Reserved	31:16	R
	Captured data for CH A	15:0	R
0x20000 to 0x2FFFC	Memory data (16k samples)
	Reserved	31:16	R
	Captured data for CH B	15:0	R

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CS[2] - Arbitrary Signal Generator (0x40200000-0x402FFFFF)

The Arbitrary Signal Generator module provides two-channel waveform generation with DMA support, burst mode, and configurable triggering.

Note

STEMlab 125-14 4-Input

On the STEMlab 125-14 4-Input board, this address space (CS[2]) contains Oscilloscope CH C and CH D instead of the Arbitrary Signal Generator.

See: CS[2] - Oscilloscope CH C/D (4-Input)

Quick Reference

Arbitrary Signal Generator Registers

Address Offset	Description	R/W
0x0	Configuration (CH A/B triggers, SM control)	R/W
0x4	CH A amplitude scale and offset	R/W
0x8-0x14	CH A counter control (wrap, offset, step, repeats)	R/W
0x18-0x20	CH A burst configuration (repetitions, delay, status)	R/W
0x24	CH B amplitude scale and offset	R/W
0x28-0x34	CH B counter control (wrap, offset, step, repeats)	R/W
0x38-0x40	CH B burst configuration (repetitions, delay, status)	R/W
0x44-0x48	CH A/B last sample value output	R/W
0x54	External trigger debouncer	R/W
0x68-0x6C	CH A/B initial generator value	R/W
0x70-0x74	CH A/B last value state length	R/W
0x78-0x7C	CH A/B LFSR random seed	R/W
0x80-0x84	CH A/B noise generator enable	R/W
0xAC	IRQ Mask	R/W
0xB0	IRQ Status / Clear	R/W
0xB4	Split IRQ Mask (independent mode)	R/W
0xB8	Split IRQ Status / Clear	R/W
0x220-0x224	Global Timestamp Counter	R
0x228-0x234	Trigger Timestamps (CH1/CH2)	R
0x100	AXI interface state (FIFO status for both channels)	R
0x104-0x10C	CH A AXI receiver control (enable, buffer addresses)	R/W
0x114-0x11C	CH B AXI receiver control (enable, buffer addresses)	R/W
0x120-0x124	CH A AXI error and transfer counts	R
0x128-0x12C	CH B AXI error and transfer counts	R
0x130-0x134	CH A/B AXI output decimation	R/W
0x10000-0x1FFFC	CH A memory data buffer (16k samples)	R/W
0x20000-0x2FFFC	CH B memory data buffer (16k samples)	R/W

Configuration and Control

Configuration and Trigger Control

Offset	Description	Bits	R/W
0x0	Configuration
	Reserved	31:25	R
	CH B external gated repetitions	24	R/W
	CH B set output to 0	23	R/W
	CH B SM reset	22	R/W
	CH B Use last sample	21	R/W
	CH B SM wrap pointer (if disabled starts at address 0)	20	R/W
	CH B trigger selector (don’t change when SM is active): 1 - Trig immediately 2 - External trigger positive edge - DIO0_P pin 3 - External trigger negative edge	19:16	R/W
	Reserved	15:9	R
	CH A external gated bursts	8	R/W
	CH A set output to 0	7	R/W
	CH A SM reset	6	R/W
	CH A Use last sample	5	R/W
	CH A SM wrap pointer (if disabled starts at address 0)	4	R/W
	CH A trigger selector (don’t change when SM is active): 1 - Trig immediately 2 - External trigger positive edge - DIO0_P pin 3 - External trigger negative edge	3:0	R/W
0x54	External trigger debouncer
	Number of ADC clock periods trigger is disabled after activation. Default value is decimal 62500 or equivalent to 0.5 ms	19:0	R/W

Channel A Signal Generation

Offset	Description	Bits	R/W
0x4	CH A amplitude scale and offset
	out = (data*scale)/0x2000 + offset
	Reserved	31:30	R
	Amplitude offset	29:16	R/W
	Reserved	15:14	R
	Amplitude scale. Unsigned	13:0	R/W
	0x2000 == multiply by 1
0x8	CH A counter wrap
	Reserved	31:30	R
	Value where counter wraps around (16 bits for decimals). Depends on SM wrap setting: * 1 - New value is acquired by wrap * 0 - Counter goes to offset value	29:0	R/W
0xC	CH A start offset
	Reserved	31:30	R
	Counter start offset (16 bits for decimals). Start offset when trigger arrives.	29:0	R/W
0x10	CH A counter step
	Reserved	31:30	R
	Counter step (16 bits for decimals). Updates when writing to the CH B counter step reg.	29:0	R/W
0x14	CH A counter step- lower bits
	Counter step extra 32 decimals. Updates when writing to the CH B counter step lower bits reg (0x34).	31:0	R/W
0x18	CH A number of read cycles in one burst (NCYC)
	Reserved	31:16	R
	Number of repeats of table readout (NCYC): 0 - Disable burst mode X - X repeats 65535 (0xffff) - 65535 repeats (max value)	15:0	R/W
0x1C	CH A number of burst repetitions (NOR)
	Reserved	31:16	R
	Number of repetitions (NOR): 0 - 1 repetition X - X+1 repetitions 65535 (0xffff) - infinite (max value)	15:0	R/W
0x20	CH A delay between burst repetitions
	Delay between repetitions. Granularity = 1 us	31:0	R/W
0x44	CH A value of last sample in burst
	Last value of burst	31:0	R/W
0x68	CH A initial value of generator
	First value	31:0	R/W
0x70	CH A length of last value state
	Length of last value state (in ADC periods)	31:0	R/W
0x78	CH A LFSR random seed
	Random number seed for linear-feedback shift register	31:0	R/W
0x80	CH A enable noise generator
	Reserved	31:1	R
	Enable pseudo-random noise generator	0	R/W

Channel B Signal Generation

Offset	Description	Bits	R/W
0x24	CH B amplitude scale and offset
	out = (data*scale)/0x2000 + offset
	Reserved	31:30	R
	Amplitude offset	29:16	R/W
	Reserved	15:14	R
	Amplitude scale. Unsigned	13:0	R/W
	0x2000 == multiply by 1
0x28	CH B counter wrap
	Reserved	31:30	R
	Value where counter wraps around (16 bits for decimals). Depends on SM wrap setting: * 1 - New value is acquired by wrap * 0 - Counter goes to offset value	29:0	R/W
0x2C	CH B start offset
	Reserved	31:30	R
	Counter start offset (16 bits for decimals). Start offset when trigger arrives.	29:0	R/W
0x30	CH B counter step
	Reserved	31:30	R
	Counter step (16 bits for decimals). Updates when writing to the CH B counter step reg.	29:0	R/W
0x34	CH B counter step- lower bits
	Counter step extra 32 decimals. Updates when writing to the CH B counter step lower bits reg (0x34).	31:0	R/W
0x38	CH B number of read cycles in one burst (NCYC)
	Reserved	31:16	R
	Number of repeats of table readout (NCYC): 0 - Disable burst mode X - X repeats 65535 (0xffff) - 65535 repeats (max value)	15:0	R/W
0x3C	CH B number of burst repetitions (NOR)
	Reserved	31:16	R
	Number of repetitions (NOR): 0 - 1 repetition X - X+1 repetitions 65535 (0xffff) - infinite (max value)	15:0	R/W
0x40	CH B delay between burst repetitions
	Delay between repetitions. Granularity = 1 us	31:0	R/W
0x48	CH B value of last sample in burst
	Last value of burst	31:0	R/W
0x6C	CH B initial value of generator
	First value	31:0	R/W
0x74	CH B length of last value state
	Length of last value state (in ADC periods)	31:0	R/W
0x7C	CH B LFSR random seed
	Random number seed for linear-feedback shift register	31:0	R/W
0x84	CH B enable noise generator
	Reserved	31:1	R
	Enable pseudo-random noise generator	0	R/W

AXI Interface Control

Offset	Description	Bits	R/W
0x100	AXI interface ASG state
	Reserved	31:20	R
	FIFOs being reset CH B	19	R
	Receive FIFO reading enabled CH B	18	R
	First data read out to output CH B	17	R
	Trigger received, generating read requests CH B	16	R
	Reserved	15:4	R
	FIFOs being reset CH A	3	R
	Receive FIFO reading enabled CH A	2	R
	First data read out to output CH A	1	R
	Trigger received, generating read requests CH A	0	R
0x104	CH A enable AXI receiver
	Reserved	31:1	R
	Enable AXI receiver	0	R/W
0x108	CH A AXI receiver buffer start address
	Buffer start address. Reads are performed in chunks of 16*64 bit. The buffer size must therefore be N*0x80.	31:0	R/W
0x10C	CH A AXI receiver buffer end address
	Buffer end address. Read pointer cannot pass this address. The last read is performed at [VALUE of this reg]-8 before wrapping around	31:0	R/W
0x114	CH B enable AXI receiver
	Reserved	31:1	R
	Enable AXI receiver	0	R/W
0x118	CH B AXI receiver buffer start address
	Buffer start address. Reads are performed in chunks of 16*64 bit. The buffer size must therefore be N*0x80.	31:0	R/W
0x11C	CH B AXI receiver buffer end address
	Buffer end address. Read pointer cannot pass this address. The last read is performed at [VALUE of this reg]-8 before wrapping around	31:0	R/W
0x120	CH A AXI error count
	Number of attempted empty FIFO reads per second	31:0	R
0x124	CH A AXI transfer count
	Number of successful FIFO reads per second	31:0	R
0x128	CH B AXI error count
	Number of attempted empty FIFO reads per second	31:0	R
0x12C	CH B AXI transfer count
	Number of successful FIFO reads per second	31:0	R
0x130	CH A AXI output decimation
	How many clocks to keep a sample on the output	31:0	R/W
0x134	CH B AXI output decimation
	How many clocks to keep a sample on the output	31:0	R/W

Memory Data Buffers

Offset	Description	Bits	R/W
0x10000 to 0x1FFFC	CH A memory data (16k samples)
	CH A data	31:0	R/W
0x20000 to 0x2FFFC	CH B memory data (16k samples)
	CH B data	31:0	R/W

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CS[3] - PID Controller (0x40300000-0x403FFFFF)

The PID Controller module provides four PID controllers (PID11, PID12, PID21, PID22) for feedback control applications.

Quick Reference

Offset	Register	R/W
0x0	Configuration (integrator reset for all PIDs)	R/W
0x10-0x1C	PID11 parameters (set point, Kp, Ki, Kd)	R/W
0x20-0x2C	PID12 parameters (set point, Kp, Ki, Kd)	R/W
0x30-0x3C	PID21 parameters (set point, Kp, Ki, Kd)	R/W
0x40-0x4C	PID22 parameters (set point, Kp, Ki, Kd)	R/W

Configuration

Offset	Description	Bits	R/W
0x0	Configuration
	Reserved	31:4	R
	PID22 integrator reset	3	R/W
	PID21 integrator reset	2	R/W
	PID12 integrator reset	1	R/W
	PID11 integrator reset	0	R/W

PID11 Controller

Offset	Description	Bits	R/W
0x10	PID11 set point
	Reserved	31:14	R
	PID11 set point	13:0	R/W
0x14	PID11 proportional coefficient
	Reserved	31:14	R
	PID11 Kp	13:0	R/W
0x18	PID11 integral coefficient
	Reserved	31:14	R
	PID11 Ki	13:0	R/W
0x1C	PID11 derivative coefficient
	Reserved	31:14	R
	PID11 Kd	13:0	R/W

PID12 Controller

Offset	Description	Bits	R/W
0x20	PID12 set point
	Reserved	31:14	R
	PID12 set point	13:0	R/W
0x24	PID12 proportional coefficient
	Reserved	31:14	R
	PID12 Kp	13:0	R/W
0x28	PID12 integral coefficient
	Reserved	31:14	R
	PID12 Ki	13:0	R/W
0x2C	PID12 derivative coefficient
	Reserved	31:14	R
	PID12 Kd	13:0	R/W

PID21 Controller

Offset	Description	Bits	R/W
0x30	PID21 set point
	Reserved	31:14	R
	PID21 set point	13:0	R/W
0x34	PID21 proportional coefficient
	Reserved	31:14	R
	PID21 Kp	13:0	R/W
0x38	PID21 integral coefficient
	Reserved	31:14	R
	PID21 Ki	13:0	R/W
0x3C	PID21 derivative coefficient
	Reserved	31:14	R
	PID21 Kd	13:0	R/W

PID22 Controller

Offset	Description	Bits	R/W
0x40	PID22 set point
	Reserved	31:14	R
	PID22 set point	13:0	R/W
0x44	PID22 proportional coefficient
	Reserved	31:14	R
	PID22 Kp	13:0	R/W
0x48	PID22 integral coefficient
	Reserved	31:14	R
	PID22 Ki	13:0	R/W
0x4C	PID22 derivative coefficient
	Reserved	31:14	R
	PID22 Kd	13:0	R/W

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CS[4] - Analog Mixed Signals (0x40400000-0x404FFFFF)

The Analog Mixed Signals (AMS) module provides access to XADC inputs and PWM DAC outputs.

Quick Reference

Offset	Register	R/W
0x0-0x10	XADC analog inputs (AIF0-AIF4, 5V)	R
0x20-0x2C	PWM DAC outputs (DAC0-DAC3)	R/W

XADC Analog Inputs

Offset	Description	Bits	R/W
0x0	XADC AIF0
	Reserved	31:12	R
	AIF0 value	11:0	R
0x4	XADC AIF1
	Reserved	31:12	R
	AIF1 value	11:0	R
0x8	XADC AIF2
	Reserved	31:12	R
	AIF2 value	11:0	R
0xC	XADC AIF3
	Reserved	31:12	R
	AIF3 value	11:0	R
0x10	XADC AIF4
	Reserved	31:12	R
	AIF4 value (5V power supply)	11:0	R

PWM DAC Outputs

Offset	Description	Bits	R/W
0x20	PWM DAC0
	Reserved	31:24	R
	PWM value (100% == 255)	23:16	R/W
	Bit select for PWM repetition that has value PWM+1	15:0	R/W
0x24	PWM DAC1
	Reserved	31:24	R
	PWM value (100% == 255)	23:16	R/W
	Bit select for PWM repetition that has value PWM+1	15:0	R/W
0x28	PWM DAC2
	Reserved	31:24	R
	PWM value (100% == 255)	23:16	R/W
	Bit select for PWM repetition that has value PWM+1	15:0	R/W
0x2C	PWM DAC3
	Reserved	31:24	R
	PWM value (100% == 255)	23:16	R/W
	Bit select for PWM repetition that has value PWM+1	15:0	R/W

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CS[5] - Daisy Chain (0x40500000-0x405FFFFF)

The Daisy Chain module enables synchronization between multiple Red Pitaya boards.

Quick Reference

Offset	Register	R/W
0x0	Control (TX/RX enable)	R/W
0x4	Transmitter data selector	R/W
0x8	Receiver training control and status	R/W
0xC	Received data	R
0x10	Testing control (counter reset)	R/W
0x14	Testing error counter	R
0x18	Testing data counter	R

Control and Configuration

Offset	Description	Bits	R/W
0x0	Control
	Reserved	31:2	R
	RX enable	1	R/W
	TX enable	0	R/W
0x4	Transmitter data selector
	Custom data	31:16	R/W
	Reserved	15:4	R
	Data source: * 0 - data is 0 * 1 - user data (from logic) * 2 - custom data (from this register) * 3 - training data (0x00FF) * 4 - transmit received data (loop back) * 5 - random data (for testing)	3:0	R/W

Receiver

Offset	Description	Bits	R/W
0x8	Receiver training
	Reserved	31:2	R
	Training successful	1	R
	Enable training	0	R/W
0xC	Received data
	Received data that is different than 0	31:16	R
	Received raw data	15:0	R

Testing

Offset	Description	Bits	R/W
0x10	Testing control
	Reserved	31:1	R
	Reset testing counters (error & data)	0	R/W
0x14	Testing error counter
	Error counter increments if received data does not match transmitted testing data	31:0	R
0x18	Testing data counter
	Counter increments when non-zero value is received	31:0	R

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CS[6] - E3 Connector Serial Lines Test (0x40600000-0x406FFFFF)

Note

STEMlab 125-14 PRO Z7020 Gen 2 only.

Quick Reference

Offset	Register	R/W
0x0	Control (TX/RX enable)	R/W
0x4	Transmitter data selector	R/W
0x8	Receiver training control and status	R/W
0xC	Received data Line 0	R
0x10	Testing control (counter reset)	R/W
0x14-0x18	Line 0 testing counters (error, data)	R
0x20	Received data Line 1	R
0x24-0x28	Line 1 testing counters (error, data)	R
0x2C	Received data Line 2	R
0x30-0x34	Line 2 testing counters (error, data)	R
0x38	Received data Line 3	R
0x3C-0x40	Line 3 testing counters (error, data)	R

Control and Configuration

Offset	Description	Bits	R/W
0x0	Control
	Reserved	31:2	R
	RX enable	1	R/W
	TX enable	0	R/W
0x4	Transmitter data selector
	Custom data	31:1	R/W
	Reserved	15:8	R
	Data source * 0 - data is 0 * 1 - user data (from logic) * 2 - custom data (from this register) * 3 - training data (0x00FF) * 4 - transmit received data (loop back) * 5 - random data (for testing)	3:0	R/W
0x8	Receiver training
	Reserved	31:2	R
	Training successful	1	R
	Enable training	0	R/W
0xC	Received data Line 0
	Received data which is different than 0	31:1	R
	Received raw data	15:0	R
0x10	Testing control
	Reserved	31:1	R
	Reset testing counters (error & data)	0	R/W
0x14	Testing error counter Line 0
	Error counter increments if received data does not match transmitted testing data	31:0	R
0x18	Testing data counter Line 0
	Counter increments when non-zero value is received	31:0	R

Line 1 Testing

Offset	Description	Bits	R/W
0x20	Received data Line 1
	Received data that is different than 0	31:1	R
	Received raw data	15:0	R
0x24	Testing error counter Line 1
	Error counter increments if received data does not match transmitted testing data	31:0	R
0x28	Testing data counter Line 1
	Counter increments when non-zero value is received	31:0	R

Line 2 Testing

Offset	Description	Bits	R/W
0x2C	Received data Line 2
	Received data that is different than 0	31:1	R
	Received raw data	15:0	R
0x30	Testing error counter Line 2
	Error counter increments if received data does not match transmitted testing data	31:0	R
0x34	Testing data counter Line 2
	Counter increments when non-zero value is received	31:0	R

Line 3 Testing

Offset	Description	Bits	R/W
0x38	Received data Line 3
	Received data that is different than 0	31:1	R
	Received raw data	15:0	R
0x3C	Testing error counter Line 3
	Error counter increments if received data does not match transmitted testing data	31:0	R
0x40	Testing data counter Line 3
	Counter increments when non-zero value is received	31:0	R

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CS[7] - Power Test (0x40700000-0x407FFFFF)

The Power Test module is used for power consumption testing.

Quick Reference

Offset	Register	R/W
0x0	Control (enable module)	R/W

Control

Offset	Description	Bits	R/W
0x0	Control
	Reserved	31:1	R
	Enable module	0	R/W

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