CS[2] - Oscilloscope CH C/D (4-Input) (0x40200000-0x402FFFFF)
FPGA Project: v0.94
Board: STEMlab 125-14 4-Input
This document describes the CS[2] register space for the STEMlab 125-14 4-Input board. On this board, CS[2] contains Oscilloscope channels C and D instead of the Arbitrary Signal Generator found on other boards.
Note
Register Synchronization
Register writes are synchronized between channels A/B (CS[1]) and C/D (CS[2]) on the 4-Input board. The output registers are replaced with a mirrored version of the input registers for channels C/D (IN3/IN4).
Quick Reference
Address Offset |
Description |
R/W |
|---|---|---|
0x8-0xC |
CH C/D thresholds |
R/W |
0x10 |
Delay after trigger (CH C) |
R/W |
0x14 |
Data decimation (CH C) |
R/W |
0x18-0x1C |
Write pointers current/trigger (CH C) |
R |
0x20-0x24 |
CH C/D threshold hysteresis |
R/W |
0x2C |
PreTrigger counter (CH C) |
R |
0x30-0x3C |
CH C equalization filter coefficients (AA, BB, KK, PP) |
R/W |
0x40-0x4C |
CH D equalization filter coefficients (AA, BB, KK, PP) |
R/W |
0x50-0x5C |
CH C AXI DMA control (addresses, delay, enable) |
R/W |
0x60-0x64 |
CH C AXI write pointers (trigger, current) |
R |
0x70-0x7C |
CH D AXI DMA control (addresses, delay, enable) |
R/W |
0x80-0x84 |
CH D AXI write pointers (trigger, current) |
R |
0x88 |
AXI state (CH C/D status) |
R |
0x90 |
Trigger debouncer time |
R/W |
0x98 |
Reconstruction filter bypass |
R/W |
0x110 |
Delay after trigger CH D |
R/W |
0x114 |
Data decimation CH D |
R/W |
0x118-0x11C |
CH D write pointers (current, trigger) |
R |
0x12C |
PreTrigger counter CH D |
R |
0x200-0x20C |
CH C/D calibration offset and gain |
R/W |
0x220-0x224 |
Global Timestamp Counter |
R/W |
0x228-0x22C |
CH C Trigger Timestamp (LO/HI) |
R |
0x230-0x234 |
CH D Trigger Timestamp (LO/HI) |
R |
0x10000-0x1FFFC |
CH C memory data buffer (16k samples) |
R |
0x20000-0x2FFFC |
CH D memory data buffer (16k samples) |
R |
Trigger Sources
The trigger source register (0x4) accepts the following values:
Value |
Trigger Source |
|---|---|
0 |
Disabled |
1 |
Trigger immediately |
2 |
CH A threshold positive edge |
3 |
CH A threshold negative edge |
4 |
CH B threshold positive edge |
5 |
CH B threshold negative edge |
6 |
External trigger positive edge (DIO0_P pin) |
7 |
External trigger negative edge |
8 |
AWG application positive edge |
9 |
AWG application negative edge |
10 |
CH C threshold positive edge (4-Input only) |
11 |
CH C threshold negative edge (4-Input only) |
12 |
CH D threshold positive edge (4-Input only) |
13 |
CH D threshold negative edge (4-Input only) |
18 |
CH A threshold any edge |
20 |
CH B threshold any edge |
22 |
External trigger any edge |
24 |
AWG any edge |
26 |
CH C threshold any edge (4-Input only) |
28 |
CH D threshold any edge (4-Input only) |
Triggering and Acquisition Control
This section covers all registers related to triggering configuration, threshold detection, and acquisition timing.
Configuration
Offset |
Description |
Bits |
R/W |
|---|---|---|---|
0x0 |
Configuration |
Note
Configuration register (0x00) is located in CS[1] only. For CH C/D configuration, use CS[1] register bits 16-23 (CH C) and 24-31 (CH D). See main register map.
Note
Trigger source register (0x04) is located in CS[1] only. For CH C/D trigger source, use CS[1] register bytes 2 (CH C, bits 16-23) and 3 (CH D, bits 24-31). See main register map.
Trigger Source and Thresholds
Offset |
Description |
Bits |
R/W |
|---|---|---|---|
0x8 |
CH C threshold |
||
Reserved |
31:14 |
R |
|
Trigger when ADC value crosses this threshold |
13:0 |
R/W |
|
0xC |
CH D threshold |
||
Reserved |
31:14 |
R |
|
Trigger when ADC value crosses this threshold |
13:0 |
R/W |
|
0x20 |
CH C hysteresis |
||
Reserved |
31:14 |
R |
|
Threshold hysteresis - value must be outside to re-trigger |
13:0 |
R/W |
|
0x24 |
CH D hysteresis |
||
Reserved |
31:14 |
R |
|
Threshold hysteresis - value must be outside to re-trigger |
13:0 |
R/W |
Tip
Hysteresis usage: Set hysteresis to prevent trigger noise. The signal must move outside the hysteresis band before the trigger can fire again.
Trigger Timing
Offset |
Description |
Bits |
R/W |
|---|---|---|---|
0x10 |
Delay after trigger |
||
Number of decimated samples to capture after trigger |
31:0 |
R/W |
|
0x2C |
PreTrigger Counter |
||
Unsigned counter holding the number of samples captured between acquisition start and trigger. Stops incrementing at 0xffffffff (no overflow). |
31:0 |
R |
|
0x90 |
Trigger debouncer time |
||
Number of ADC clock periods trigger is disabled after activation reset value is decimal 62500 or equivalent to 0.5 ms |
19:0 |
R/W |
Note
For 4-channel boards, the value of this register must be written to both CS[1] (0x40100090) and CS[2] (0x40200090) for proper debouncer operation on all channels.
Data Processing
Offset |
Description |
Bits |
R/W |
|---|---|---|---|
0x14 |
Data decimation |
||
Reserved |
31:17 |
R |
|
|
16:0 |
R/W |
Write Pointers and Status
Offset |
Description |
Bits |
R/W |
|---|---|---|---|
0x18 |
Write pointer - current |
||
Reserved |
31:14 |
R |
|
Current write pointer |
13:0 |
R |
|
0x1C |
Write pointer - trigger |
||
Reserved |
31:14 |
R |
|
Write pointer at time when trigger arrived |
13:0 |
R |
Note
Signal average enable register (0x28) is located in CS[1] only. For CH C/D, use CS[1] register bits 16-17 (CH C) and 24-25 (CH D). See main register map.
Equalization Filters
Offset |
Description |
Bits |
R/W |
|---|---|---|---|
0x30 |
CH C Equalization filter AA |
||
Reserved |
31:18 |
R |
|
AA Coefficient |
17:0 |
R/W |
|
0x34 |
CH C Equalization filter BB |
||
Reserved |
31:25 |
R |
|
BB Coefficient |
24:0 |
R/W |
|
0x38 |
CH C Equalization filter KK |
||
Reserved |
31:25 |
R |
|
KK Coefficient |
24:0 |
R/W |
|
0x3C |
CH C Equalization filter PP |
||
Reserved |
31:25 |
R |
|
PP Coefficient |
24:0 |
R/W |
|
0x40 |
CH D Equalization filter AA |
||
Reserved |
31:18 |
R |
|
AA Coefficient |
17:0 |
R/W |
|
0x44 |
CH D Equalization filter BB |
||
Reserved |
31:25 |
R |
|
BB Coefficient |
24:0 |
R/W |
|
0x48 |
CH D Equalization filter KK |
||
Reserved |
31:25 |
R |
|
KK Coefficient |
24:0 |
R/W |
|
0x4C |
CH D Equalization filter PP |
||
Reserved |
31:25 |
R |
|
PP Coefficient |
24:0 |
R/W |
AXI DMA Configuration
Offset |
Description |
Bits |
R/W |
|---|---|---|---|
0x50 |
CH C AXI lower address |
||
Starting write address |
31:0 |
R/W |
|
0x54 |
CH C AXI upper address |
||
Address where it wraps to lower address |
31:0 |
R/W |
|
0x58 |
CH C AXI delay after trigger |
||
Number of decimated samples to write after trigger |
31:0 |
R/W |
|
0x5C |
CH C AXI enable master |
||
Reserved |
31:1 |
R |
|
Enable AXI master |
0 |
R/W |
|
0x60 |
CH C AXI write pointer - trigger |
||
Write pointer at time when trigger arrived |
31:0 |
R |
|
0x64 |
CH C AXI write pointer - current |
||
Current write pointer |
31:0 |
R |
|
0x70 |
CH D AXI lower address |
||
Starting write address |
31:0 |
R/W |
|
0x74 |
CH D AXI upper address |
||
Address where it wraps to lower address |
31:0 |
R/W |
|
0x78 |
CH D AXI delay after trigger |
||
Number of decimated samples to write after trigger |
31:0 |
R/W |
|
0x7C |
CH D AXI enable master |
||
Reserved |
31:1 |
R |
|
Enable AXI master |
0 |
R/W |
|
0x80 |
CH D AXI write pointer - trigger |
||
Write pointer at time when trigger arrived |
31:0 |
R |
|
0x84 |
CH D AXI write pointer - current |
||
Current write pointer |
31:0 |
R |
AXI State
Offset |
Description |
Bits |
R/W |
|---|---|---|---|
0x88 |
AXI state registers |
||
Reserved |
31:21 |
R |
|
CH D AXI - Acquisition delay complete (all data written to buffer) |
20 |
R |
|
CH D AXI - Trigger remains armed after acquisition delay completes |
19 |
R |
|
CH D AXI - Trigger has arrived |
18 |
R |
|
Reserved |
17 |
R |
|
CH D AXI - Trigger armed |
16 |
R |
|
Reserved |
15:5 |
R |
|
CH C AXI - Acquisition delay complete (all data written to buffer) |
4 |
R |
|
CH C AXI - Trigger remains armed after acquisition delay completes |
3 |
R |
|
CH C AXI - Trigger has arrived |
2 |
R |
|
Reserved |
1 |
R |
|
CH C AXI - Trigger armed |
0 |
R |
Channel D Specific Registers
Offset |
Description |
Bits |
R/W |
|---|---|---|---|
0x110 |
Delay after trigger CH D |
||
Number of decimated samples to write after trigger |
31:0 |
R/W |
|
0x114 |
Data decimation CH D |
||
Reserved |
31:17 |
R |
|
|
16:0 |
R/W |
|
0x118 |
Write pointer - current CH D |
||
Reserved |
31:14 |
R |
|
Current write pointer |
13:0 |
R |
|
0x11C |
Write pointer - trigger CH D |
||
Reserved |
31:14 |
R |
|
Write pointer at time when trigger arrived |
13:0 |
R |
|
0x12C |
PreTrigger Counter CH D |
||
Unsigned counter holding the number of samples captured between acquisition start and trigger. Stops incrementing at 0xffffffff (no overflow) |
31:0 |
R |
Calibration Registers
Offset |
Description |
Bits |
R/W |
|---|---|---|---|
0x200 |
CH C calibration offset |
||
Reserved |
31:16 |
R |
|
Calibration offset (16 bit signed) |
15:0 |
R/W |
|
0x204 |
CH C calibration gain |
||
Reserved |
31:16 |
R |
|
Calibration gain (16 bit signed) |
15:0 |
R/W |
|
0x208 |
CH D calibration offset |
||
Reserved |
31:16 |
R |
|
Calibration offset (16 bit signed) |
15:0 |
R/W |
|
0x20C |
CH D calibration gain |
||
Reserved |
31:16 |
R |
|
Calibration gain (16 bit signed) |
15:0 |
R/W |
Timestamp Registers
Offset |
Description |
Bits |
R/W |
|---|---|---|---|
0x220 |
Global Timestamp Counter LO |
||
Lower 32 bits of the global 64-bit timer. IMPORTANT: Reading this register latches (snapshots) the full 64-bit counter value into a temporary buffer. Always read LO first. |
|||
Global timestamp counter bits [31:0] |
31:0 |
R |
|
0x224 |
Global Timestamp Counter HI |
||
Upper 32 bits of the global 64-bit timer. Returns the upper 32 bits of the value latched when LO was read. |
|||
Global timestamp counter bits [63:32] |
31:0 |
R |
|
0x228 |
CH C Trigger Timestamp LO |
||
Lower 32 bits of the timestamp captured at the last CH C trigger event. |
|||
CH C trigger timestamp bits [31:0] |
31:0 |
R |
|
0x22C |
CH C Trigger Timestamp HI |
||
Upper 32 bits of the timestamp captured at the last CH C trigger event. |
|||
CH C trigger timestamp bits [63:32] |
31:0 |
R |
|
0x230 |
CH D Trigger Timestamp LO |
||
Lower 32 bits of the timestamp captured at the last CH D trigger event. |
|||
CH D trigger timestamp bits [31:0] |
31:0 |
R |
|
0x234 |
CH D Trigger Timestamp HI |
||
Upper 32 bits of the timestamp captured at the last CH D trigger event. |
|||
CH D trigger timestamp bits [63:32] |
31:0 |
R |
Note
For 4-channel boards, the global counter registers (0x220–0x224) must be written to both CS[1] (0x40100220) and CS[2] (0x40200220) for timestamp synchronization between channel pairs A/B and C/D.
Memory Data Buffers
Offset |
Description |
Bits |
R/W |
|---|---|---|---|
0x10000 to 0x1FFFC |
Memory data (16k samples) |
||
Reserved |
31:16 |
R |
|
Captured data for CH C |
15:0 |
R |
|
0x20000 to 0x2FFFC |
Memory data (16k samples) |
||
Reserved |
31:16 |
R |
|
Captured data for CH D |
15:0 |
R |