STEMlab 125-14 4-Input

Overview

STEMlab 125-14 4-Input is a specialized single-board RF signal acquisition platform offering 4 analog input channels instead of the standard 2 inputs and 2 outputs configuration. The board features improved RF performance with reduced crosstalk, noise, and distortions, and a more powerful Zynq 7020 FPGA compared to the standard STEMlab 125-14. The integrated CLK_SEL control pin on the E2 connector connector enables seamless switching between the on-board oscillator and an external clock source without any hardware modification.

Key Differences from Standard STEMlab 125-14

• 4 analog input channels @ 125 MS/s & 14-bit (instead of 2 inputs + 2 outputs)

• No RF outputs — all SMA connectors dedicated to inputs

• Improved RF performance: Reduced crosstalk, noise, and distortions

• Zynq 7020 FPGA: More processing capability and 22 digital I/O pins (vs 16 on 7010 boards)

• External clock support: Hardware-integrated with CLK_SEL pin (pin 21 on E2 connector) — no hardware modification required

Features

• 14-bit, 125 MS/s ADC with 4 input channels

• No analog RF outputs (all channels dedicated to inputs)

• Improved RF input performance (reduced crosstalk, noise, distortions)

• Dual-core ARM Cortex-A9 processor

• FPGA Xilinx Zynq 7020 SoC

• 512 MB RAM

• 22 digital I/Os (6 more than standard Zynq 7010 boards)

• 4 analog inputs and 4 analog outputs on extension connector

• External clock input with hardware-selectable clock source (CLK_SEL pin)

• Multiple communication interfaces: I2C, SPI, UART, CAN

Quick Reference

Category	Key Specifications
ADC	4 channels, 14-bit, 125 MS/s, DC-60 MHz
DAC	None (no RF outputs)
Processor	Dual-core ARM Cortex-A9
FPGA	Xilinx Zynq 7020 SoC
RAM	512 MB
Digital I/O	22 GPIOs @ 3.3V
Analog I/O	4 inputs (12-bit), 4 outputs (8-bit)
Connectivity	Ethernet, USB, Extension connectors
Special Features	External ADC clock

Board Layout & Pinout

Technical Specifications

Parameter	Value	Units	Notes
Basic
Processor	Dual core ARM Cortex-A9	-
FPGA	FPGA AMD (Xilinx) Zynq 7020 SoC	-
RAM	512	MB	(4 Gb)
Core clock frequency	125	MHz
System memory	Micro SD up to 32 GB	-
Serial console connector	Micro USB	-
Power connector	Micro USB	-
Power consumption	5 V, 2 A	-	max
Connectivity
Ethernet	1	Gbit
USB	USB-A 2.0	-
Wi-Fi	Requires Wi-Fi dongle	-
RF inputs
RF input channels	4	-
Sampling rate	125	MS/s
ADC resolution	14	bit
Input impedance	1 MΩ / 10 pF	-
Full scale voltage range	±1 (LV) ±20 (HV)	V
Input coupling	DC	-
Absolute max. input voltage	±6 (LV) ±30 (HV)	V	DC values [1]
Input ESD protection	1500	V	DC
Overload protection	Protection diodes	-
Bandwidth	DC - 60	MHz
Connector type	SMA	-
RF outputs
RF output channels	N/A	-
Sampling rate	N/A	-
DAC resolution	N/A	-
Load impedance	N/A	-
Voltage range	N/A	-
Output coupling	N/A	-
Short circuit protection	N/A	-
Output slew rate	N/A	-
Bandwidth	N/A	-
Connector type	N/A	-
Extension connectors
Digital GPIOs	22	-
Digital voltage levels	3.3	V
Analog inputs	4	-
Analog input voltage range	0 - 7.0	V
Analog input resolution	12	bit
Analog input sampling rate	100	kS/s
Analog outputs	4	-
Analog output voltage range	0 - 1.8	V
Analog output resolution	8	bit
Analog output sampling rate	≲ 3.2	MS/s
Analog output bandwidth	≈ 160	kHz
Communication interfaces	I2C, SPI, UART, CAN	-
Available voltages	+5, ±3.3	V
External ADC clock	Yes	-	CLK_SEL pin on E2 connector
Synchronisation
External trigger input	DIO0_P	-	E1 connector
External trigger input impedance	Hi-Z	-	Digital input
Trigger output	DIO0_N	-	E1 connector [2]
Daisy chain connectors (S1 & S2)	Yes	-
Daisy chain connectors speed	up to 500	Mb/s
Daisy chain connectors type	SATA	-
Ref. clock input	Yes [3]	-	Requires hardware modification
Ref. clock frequency	10	MHz	Requires hardware modification
Ref. clock connector type	2-pin header	-	Requires hardware modification
Boot options
SD card	Yes	-
QSPI	Not populated	-
eMMC	N/A	-
Environmental Specifications
Operating Temperature Range	0 to 55	℃	With default heatsink
Operating Humidity Range	< 90%	RH
Automatic Shutdown Temperature	85	℃
Dimensions
Size (L x W x H)	106.8 x 60.0 x 21.1	mm	See Schematics for details

See also

For more detailed information, please refer to the Original Gen board comparison table.

Warning

Maximum Input Voltage

• LV mode: ±6 V absolute maximum

• HV mode: ±30 V absolute maximum

Exceeding these values may damage the board permanently.

Performance & Measurements

Note

Although specific measurements for the STEMlab 125-14 4-Input board have not been published, it is expected to fall within the measurement range of the STEMlab 125-14 and STEMlab 125-14 Gen 2 boards. The 4-Input board was produced immediately prior to the STEMlab 125-14 Gen 2 and incorporates some of the Gen 2 analog front-end improvements.

You can find the measurements of the fast analog frontend here:

• Original Gen - STEMlab 125-14.

• Gen 2 - STEMlab 125-14 Gen 2.

Schematics & 3D Models

Schematics

• Schematics_STEM_125-14-4_IN_V1r3.pdf.

Note

Full hardware schematics for the Red Pitaya board are not available. Red Pitaya has open-source code but not open hardware schematics. Nonetheless, development schematics are available. This schematic will give you information about hardware configuration, FPGA pin connections, and similar.

Mechanical Specifications & 3D Models

• STEP 3D_STEM_125-14-4_IN_V1r3.zip.

Hardware Details

Components

ADC: Analog Devices LTC2145-14

• Dual 14-bit, 125 MS/s ADC

• Low noise and distortion

• High dynamic range

Note

The 4-Input board uses two LTC2145-14 ADC chips to achieve 4 input channels.

FPGA: Xilinx Zynq 7020

• Dual-core ARM Cortex-A9 @ 667 MHz

• Larger programmable logic fabric than Zynq 7010

• 22 digital I/Os on the E1 extension connector

Oscillator: IQ3309 125 MHz

• Provides the default ADC clock

• Bypassed when CLK_SEL = GND (external clock mode)

Extension Connectors & Interfaces

Overview

The STEMlab 125-14 4-Input board features the following connectors and interfaces:

• E1 and E2 connectors: Primary expansion connectors with digital I/O, analog I/O, and communication interfaces. These connectors allow users to interface with additional hardware, sensors, or peripherals.

• S1 and S2 connectors: SATA connectors connected directly to the FPGA. Unlike the STEMlab 125-14, this board does not support multi-board clock synchronisation through these connectors — the shared clock signal does not propagate to the ADC and DAC. They can still be used to exchange clock, trigger, or data signals between boards or external devices. Note that the voltage levels are 1V8, which is non-standard for SATA connections.

Connector Physical Specifications

E1 and E2 Extension Connectors:

• Connector type: 2 x 13 pins IDC 2.54 mm pitch

• Pin count: 26 pins each (2x13 configuration)

• Pitch: 2.54 mm (0.1”)

Mating Connectors:

Note

When looking for mating connectors for custom Red Pitaya shields, double height elevated sockets are needed to clear the heatsink and ethernet connector on the board. Any connectors with insulation height of 0.635” (16.13 mm) or greater will work. This clearance requirement is based on the tallest components on the Red Pitaya board (heatsink and ethernet connector).

Note

To prevent damage to the board or the shield, when connecting shields to the E1 and E2 connectors, please ensure:

• Proper alignment of connectors - ensure the connectors are correctly aligned. The connectors on the Red Pitaya board have additional space in the socket housing, making it possible to misalign the shields by ±1 pin while still appearing physically connected. This can cause damage to the board and/or the shield, so please double-check the alignment before powering on the board.

• Tight-fitting counterparts - use connectors that fit securely to prevent accidental disconnections or damage.

E1 Connector - Digital I/O & CAN

The E1 extension connector provides digital I/O and CAN bus interfaces for control and communication applications.

Features:

• Two +3V3 power sources (max 0.5 A of current)

• 22 single-ended or 8 differential digital I/Os with 3.3 V logic levels

• Two CAN buses (configurable via software)

Electrical Specifications:

All DIOx_y pins are LVCMOS33, with the following absolute maximum ratings:

• Min. voltage: -0.40 V

• Max. voltage: 3.3 V + 0.55 V

• Drive strength: < 8 mA

E1 Pinout:

Pin	Description	FPGA pin number	FPGA pin description	Voltage levels
1	3V3
2	3V3
3	DIO0_P / EXT TRIG	G17	IO_L16P_T2_35	3.3V
4	DIO0_N / TRIG OUT	G18	IO_L16N_T2_35	3.3V
5	DIO1_P	H16	IO_L13P_T2_MRCC_35	3.3V
6	DIO1_N	H17	IO_L13N_T2_MRCC_35	3.3V
7	DIO2_P	J18	IO_L14P_T2_AD4P_SRCC_35	3.3V
8	DIO2_N	H18	IO_L14N_T2_AD4N_SRCC_35	3.3V
9	DIO3_P	K17	IO_L12P_T1_MRCC_35	3.3V
10	DIO3_N	K18	IO_L12N_T1_MRCC_35	3.3V
11	DIO4_P	L14	IO_L22P_T3_AD7P_35	3.3V
12	DIO4_N	L15	IO_L22N_T3_AD7N_35	3.3V
13	DIO5_P	L16	IO_L11P_T1_SRCC_35	3.3V
14	DIO5_N	L17	IO_L11N_T1_SRCC_35	3.3V
15	DIO6_P / CAN1_RX	K16	IO_L24P_T3_AD15P_35	3.3V
16	DIO6_N / CAN1_TX	J16	IO_L24N_T3_AD15N_35	3.3V
17	DIO7_P / CAN0_RX	M14	IO_L23P_T3_35	3.3V
18	DIO7_N / CAN0_TX	M15	IO_L23N_T3_35	3.3V
19	DIO8_P	Y9	IO_L14P_T2_SRCC_13	3.3V
20	DIO8_N	Y8	IO_L14N_T2_SRCC_13	3.3V
21	DIO9_P	Y12	IO_L20P_T3_13	3.3V
22	DIO9_N	Y13	IO_L20N_T3_13	3.3V
23	DIO10_P	Y7	IO_L13P_T2_MRCC_13	3.3V
24	DIO10_N	Y6	IO_L13N_T2_MRCC_13	3.3V
25	GND
26	GND

Note

To change the functionality of DIO6_P, DIO6_N, DIO7_P and DIO7_N from GPIO to CAN, please modify the housekeeping register value at address 0x34. For further details, please refer to the FPGA register section.

The change can also be performed with the appropriate SCPI or API command. Please refer to the CAN commands section for further details.

E2 Connector - Analog & Communication

The E2 extension connector provides analog I/O and communication interfaces, and houses the CLK_SEL pin for switching between the on-board oscillator and an external ADC clock.

Features:

• +5 V power source (max 0.5 A, shared with USB devices)

• -3.4 V power source (max 0.05 A) [4]

• SPI, UART, I2C communication interfaces

• 4 slow ADCs (12-bit, 100 kS/s)

• 4 slow DACs (8-bit PWM, ≲ 3.2 MS/s)

• CLK_SEL pin (pin 21): GND = external clock, 3V3/floating = internal clock

• External ADC clock input on pins 23-24 (Ext. ADC Clk±)

E2 Pinout:

Pin	Description	FPGA pin number	FPGA pin description	Voltage levels
1	+5V
2	-3.4V [4]
3	SPI (MOSI)	E9	PS_MIO10_500	3V3
4	SPI (MISO)	C6	PS_MIO11_500	3V3
5	SPI (SCK)	D9	PS_MIO12_500	3V3
6	SPI (CS)	E8	PS_MIO13_500	3V3
7	UART (TX)	D5	PS_MIO8_500	3V3
8	UART (RX)	B5	PS_MIO9_500	3V3
9	I2C (SCL)	B13	PS_MIO50_501	3V3
10	I2C (SDA)	B9	PS_MIO51_501	3V3
11	Ext com. mode (AIN)			GND (default)
12	GND
13	Analog Input 0	B19, A20	IO_L2P_T0_AD8P_35, IO_L2N_T0_AD8N_35	0-7.0 V
14	Analog Input 1	C20, B20	IO_L1P_T0_AD0P_35, IO_L1N_T0_AD0N_35	0-7.0 V
15	Analog Input 2	E17, D18	IO_L3P_T0_DQS_AD1P_35, IO_L3N_T0_DQS_AD1N_35	0-7.0 V
16	Analog Input 3	E18, E19	IO_L5P_T0_AD9P_35, IO_L5N_T0_AD9N_35	0-7.0 V
17	Analog Output 0	T10	IO_L1N_T0_34	0-1.8 V
18	Analog Output 1	T11	IO_L1P_T0_34	0-1.8 V
19	Analog Output 2	P15	IO_L24P_T3_34	0-1.8 V
20	Analog Output 3	U13	IO_L3P_T0_DQS_PUDC_B_34	0-1.8 V
21	CLK_SEL			3.3V / GND
22	GND
23	Ext. ADC Clk+			LVDS
24	Ext. ADC Clk-			LVDS
25	GND
26	GND

Note

UART TX (PS_MIO08) is an output only. It must be connected to GND or left floating at power-up (no external pull-ups)!

Note

CLK_SEL pin (pin 21): Drive to GND to select external clock mode (Ext. ADC Clk± on pins 23-24). Drive to 3V3 or leave floating to use the on-board oscillator (internal clock mode).

Auxiliary Analog Inputs & Outputs

Auxiliary Analog Input Channels

The E2 connector provides 4 auxiliary analog inputs for slow-speed measurements and sensor interfacing.

Parameter	Value	Units	Notes
Number of channels	4	-
ADC resolution	12	bit
Sampling rate	100	kS/s	[5]
Input voltage range	0 - 7.0	V
Input coupling	DC	-
Connector	Extension connector E2 connector	-	Pins 13, 14, 15, 16

Auxiliary Analog Output Channels

The E2 connector provides 4 auxiliary analog outputs using PWM with low-pass filtering.

Parameter	Value	Units	Notes
Number of channels	4	-
Output resolution	8	bit
Sampling rate	≲ 3.2	MS/s
Output bandwidth	≈ 160	kHz
Output voltage range	0 - 1.8	V
Output coupling	DC	-
Output type	Low pass filtered PWM	-	[6]
PWM time resolution	8	ns	(1/125 MHz)
Connector	Extension connector E2 connector	-	Pins 17, 18, 19, 20

General Purpose Digital I/O Channels

Parameter	Value	Units	Notes
Number of GPIOs	22	-
Digital voltage level	3.3	V
Abs. min. voltage	-0.40	V
Abs. max. voltage	3.3 + 0.55	V
Current limitation	< 8	mA	Drive strength
Direction	Configurable	-
Time resolution	8	ns	(1/125 MHz)
Connector location	Extension connector E1 connector	-

Synchronisation Connectors (S1 & S2)

The Original generation Red Pitaya boards feature SATA connectors that are connected directly to the FPGA. Unlike the STEMlab 125-14, this board does not support multi-board clock synchronisation through the SATA connectors — the shared clock signal does not propagate to the ADC and DAC, so true synchronisation is not achievable this way. The connectors can still be used to exchange clock, trigger, or data signals between boards or external devices.

Synchronisation Connectors:

Parameter	Specification
Connector type	SATA
Number of connectors	2 (for daisy-chaining)
Maximum data rate	up to 500 Mb/s
Purpose	Clock and trigger sync

Note

The SATA connectors use 1V8 logic levels, which is non-standard for SATA connections. They are not compatible with standard SATA storage devices. Exercise caution when connecting external devices to these connectors to avoid damaging the board.

Advanced Features

Power Supply

Red Pitaya boards can be powered through two methods:

1. Micro USB connector

2. +5V pin (pin 1) and GND pin (pin 25, 26) on the |E2| connector

Power Supply Specifications:

Parameter	Specification
Power supply voltage	5 V
Maximum current draw	2.0 A
Power supply type	DC

Note

The board’s maximum current draw is 2.0 A. The power supply may have a higher current rating — this will not cause any issues.

The micro-USB power input includes a simple integrated protection circuit that prevents damage to the board.

Figure 4.9 Protection circuit for powering through the micro-USB connector

Warning

When powering the Red Pitaya through the extension connector (+5V pin on E2 connector), external protection must be provided by the user to protect the board from overvoltage and overcurrent conditions.

Available Power Rails on Extension Connectors:

The E1 connector and E2 connector connectors expose several power rails that can be used to supply power to external devices or circuits connected to the board. The current limits below are the maximum currents that Red Pitaya can source from each rail to external loads — they are not related to the board’s own power consumption.

Voltage Rail	Max. Sourceable Current
+5 V	0.5 A [7]
+3V3	0.5 A [7]
-3.3V / -3.4V / -4 V	0.05 A

Note

Exceeding these limits may cause voltage rail instability, which can result in a board reset or shutdown.

External ADC Clock

The main ADC, DAC, and FPGA CLK signal can be supplied from an external source through the Ext. ADC Clk± ports on the E2 connector connector.

Clock Selection

Both the internal oscillator clock and the external clock signal are connected to the NB6L72 Differential Crosspoint Switch. The CLK_SEL pin (pin 21 on E2 connector) is used to select the clock source:

• 3V3 (logic high) or unconnected: Internal clock (default), supplied from the onboard oscillator.

• GND (logic low): External clock, supplied through the Ext. ADC Clk± ports.

Signal Path

The clock signal travels from the output of the NB6L72 through the ADC to the FPGA and DAC, ensuring consistent timing across the signal acquisition path.

External Clock Specifications

The external ADC clock should comply with NB6L72 input specifications:

Parameter		Description	Min	Typ	Max	Unit
	Clock input pins	23 (Clk+) and 24 (Clk-) on E2 connector
	Input standards	LVPECL, CML, LVDS, LVCMOS, LVTTL
	Input clock coupling	AC (on-board capacitors)
\(f_{CLK}\)	Input frequency range		1		125	MHz
\(V_{ID,DIFF,PP}\)	Input voltage swing	Differential peak-to-peak	150		3300	mV
IDC	Input clock duty cycle		45%		55%

Note

The typical operating frequency depends on the board variant:

• STEMlab 125-14 Gen 2 boards: 125 MHz

Operating outside the board’s specified frequency is possible but voids all performance guarantees. See the warning below.

Note

The board includes AC coupling capacitors on the external clock inputs, so the input signal must have sufficient amplitude and slew rate to meet the NB6L72 input specifications after AC coupling.

For further information on voltage levels and timing requirements, please refer to the NB6L72 datasheet.

Warning

Not a reference clock input: The Ext. ADC Clk± ports are not a reference clock input for a PLL or any other timing circuit. They directly drive the main sampling clock for the ADC, DAC, and FPGA. Connecting a reference clock signal intended for a PLL will not function as expected.

Warning

Changing the external clock frequency during operation is not supported.

The Zynq 7010/7020 PL uses Mixed-Mode Clock Managers (MMCMs) and PLLs to derive internal fabric clocks from the input clock. Changing the external clock frequency during operation will cause the MMCM/PLL to lose lock, resulting in undefined output clocks and acquisition/generation errors. A full FPGA reset or reconfiguration is required after any clock frequency change.

Note

Operating at non-standard clock frequencies:

The Red Pitaya FPGA is designed, tested, and guaranteed to operate correctly at the board’s specified core clock frequency (125 MHz for STEMlab 125-14, 122.88 MHz for SDRlab 122-16, etc).

While it is possible to run the board at different clock frequencies, please be aware that:

1. FPGA functionality: The official FPGA configuration may not function as intended at non-standard frequencies and requires thorough testing

2. Sampling rates: The ADC and DAC sampling rates will change proportionally with the clock frequency

3. Analog bandwidth: The analog bandwidth of the board will change with the clock frequency

4. Absence of external clock:

   • OS 2.07-48 or higher: If no valid external clock is present, the PS side will boot using an internal 33 MHz oscillator, but the FPGA will not operate (no signal acquisition/generation functionality)

   • OS versions prior to 2.07-48: The board will fail to boot (stuck in reboot cycle) if no valid external clock is detected

Note

Advanced: Dynamic clock reconfiguration

The standard Red Pitaya FPGA bitstream does not implement the Dynamic Reconfiguration Port (DRP) interface that AMD (Xilinx) provides for runtime MMCM/PLL reconfiguration. A custom FPGA design using DRP-based MMCM reconfiguration with active lock monitoring could theoretically support runtime clock frequency changes, but this requires extensive FPGA development and verification. The PS side (ARM/Linux) is not affected by clock changes, as it runs from its own independent 33 MHz crystal-derived PLL.

Note

When synchronising multiple Red Pitaya boards, please keep in mind that:

• X-channel 2.0 synchronisation (Click Shields) works out-of-the-box

• X-channel synchronisation requires a hardware modification as secondary boards differ from the primary board

Locking the Oscillator to an External 10 MHz Reference

It is possible to lock the internal oscillator to an external 10 MHz clock supplied through the DIO10 differential pair (DIO10_P and DIO10_N) on the E1 connector connector.

This requires a hardware modification of the board by placing the optional Si570/Si571 VXCO (Voltage Controlled Oscillator) and locking the oscillator to the external 10 MHz clock using the FPGA.

The oscillator is synchronized through the PPL_LO (K14, IO_L20P_T3_AD6P_35) and PLL_HI (J15, IO_25_35) pins on the FPGA.

If you are interested in this feature, please contact us at support@redpitaya.com.

Calibration

Red Pitaya original generation boards are factory-calibrated. Recalibration may be required after extended use, environmental changes, or when measurement accuracy degrades.

There are three ways to calibrate the board:

• Calibration application — graphical interface accessible from the System Tools menu. Recommended for most users.

• Calibration command line utility (calib) — command line tool for scripted or advanced calibration workflows.

• C++ or Python API commands — programmatic access to calibration parameters.

For a full description of the calibration procedure, required equipment, and technical reference, please refer to the Calibration documentation.

Note

Original generation boards require 50 Ω terminators during calibration due to a mismatch in the impedance of fast analog inputs and outputs.

Additional Resources

For additional specifications and measurements, please refer to:

• Original Gen hardware specifications - Common Original Gen specifications

• Original Gen board comparison table - Comparison across all Red Pitaya Original Gen models

Legal & Disclaimers

Note

The information provided by Red Pitaya d.o.o. is believed to be accurate and reliable. However, no liability is accepted for its use. Please note that the contents may be subject to change without prior notice.

Footnotes

[1]

The absolute maximum input voltage values are for frequencies below 1 kHz. For higher frequencies, please use the input voltage range specifications as Absolute maximum.

[2]

See the X-channel 2.0 (Click Shield) synchronisation and X-channel 2.0 (Click Shield) synchronisation examples.

[3]

This feature requires a hardware modification of the board by placing the optional VXCO. See the Locking the Oscillator to an External 10 MHz Reference section for more details.

[4] (1,2)

In older board revisions, the supply voltage on pin 2 may be labelled -3.3 V. The actual measured voltage is typically -3.4 V.

[5]

The default software enables sampling at a CPU-dependent speed. To acquire data at a 100 kS/s rate, additional FPGA processing must be implemented.

[6]

The output is passed through a first-order low-pass filter. Should additional filtering be required, this can be applied externally in line with the specific requirements of the application.

[7] (1,2)

Application specific. The output current is shared between the extension connectors and the connected USB devices, and can be higher if other peripheral units are not in use.