Stream App 250 FPGA Project

FPGA Project: stream_app_250

Compatible Boards:

  • STEMlab 250-12

Compatible applications:

The Stream App 250 FPGA project provides high-speed data streaming capabilities for Red Pitaya STEMlab 250-12. It enables continuous ADC and DAC data streaming with configurable triggering, decimation, filtering, and DMA-based data transfer.


Memory Map Overview

Start

End

Module Name

CS[0]

0x40000000

0x400FFFFF

ADC streaming (IN)

CS[1]

0x40100000

0x401FFFFF

DAC streaming (OUT)

CS[2]

0x40200000

0x402FFFFF

GPIO streaming (IN/OUT)

CS[0] - ADC Streaming (0x40000000-0x400FFFFF)

The ADC Streaming module provides real-time data acquisition with DMA support, triggering, decimation, and filtering capabilities.

Quick Reference

Offset

Register

R/W

0x0-0x8

Event control (status, select, trigger mask)

R/W

0x10-0x28

Trigger configuration (pre/post samples, levels, edge)

R/W

0x30-0x44

Data processing (decimation, averaging, filter, 8-bit)

R/W

0x50-0x70

DMA configuration (control, status, buffers)

R/W

0x74-0x80

Calibration (offset and gain for CH1/CH2)

R/W

0x9C-0xA8

Lost samples counters and write pointers (CH2)

R

0xC0-0xDC

Equalization filter coefficients (CH1/CH2)

W

0x100

Board status (clock, mode)

R

Event Control

Offset

Description

Bits

R/W

0x0

Event status register

Reserved

31:4

R

Trigger event

3

R/W

Stop event

2

R/W

Start event

1

R/W

Reset event

0

R/W

0x4

Event select register

Reserved

31:5

R

Logic analyser event

4

W

Scope CH2 event

3

W

Scope CH1 event

2

W

Signal generator CH2 event

1

W

Signal generator CH1 event

0

W

Trigger Configuration

Offset

Description

Bits

R/W

0x8

Trigger mask

Reserved

31:6

R

External board trigger

5

W

Logic analyser trigger

4

W

Scope CH2 trigger

3

W

Scope CH1 trigger

2

W

Signal generator CH2 trigger

1

W

Signal generator CH1 trigger

0

W

0x10

Trigger pre samples

Number of pre-trigger samples

31:0

W

0x14

Trigger post samples

Number of post-trigger samples

31:0

W

0x18

Trigger pre counter

Actual count of pre-trigger samples

31:0

R

0x1C

Trigger post counter

Actual count of post-trigger samples

31:0

R

0x20

Trigger low level

Reserved

31:16

R

Low trigger level

15:0

W

0x24

Trigger high level

Reserved

31:16

R

High trigger level

15:0

W

0x28

Trigger edge

Reserved

31:1

R
Trigger edge:

  • 0 - Rising edge

  • 1 - Falling edge

0

W

Data Processing

Offset

Description

Bits

R/W

0x30

Decimation factor

Reserved

31:17

R

Decimation factor

16:0

W

0x34

Decimation right shift

Reserved

31:4

R

Decimation right shift

3:0

W

0x38

Averaging enable

Reserved

31:1

R
Averaging enable:

  • 0 - Disabled

  • 1 - Enabled

0

W

0x3C

Filter bypass

Reserved

31:1

R
Filter bypass:

  • 0 - Disabled

  • 1 - Enabled

0

W

0x40

Digital loopback

Reserved

31:21

R

Use ramp signal ADC CH4

20

R/W

Reserved

19:17

R

Use ramp signal ADC CH3

16

R/W

Reserved

15:13

R

Use ramp signal ADC CH2

12

R/W

Reserved

11:9

R

Use ramp signal ADC CH1

8

R/W

ADC CH2

7:6

R

Loopback DAC CH2

5

R/W

Loopback GPIO N

4

R/W

ADC CH1

3:2

R

Loopback DAC CH1

1

R/W

Loopback GPIO P

0

R/W

0x44

Resolution select

Reserved

31:1

R
Resolution select:

  • 0 - 16 bit resolution

  • 1 - 8 bit resolution

0

W

DMA Configuration

Offset

Description

Bits

R/W

0x50

DMA control register

Reserved

31:10

R

Streaming DMA mode

9

W

Normal DMA mode

8

W

Reserved

7:5

R

Reset buffers and flags

4

W

Buffer 2 acknowledge

3

W

Buffer 1 acknowledge

2

W

Interrupt acknowledge

1

W

Start DMA

0

W

0x54

DMA status register

Reserved

31:4

R

Buffer 2 overflow

3

R

Buffer 1 overflow

2

R

Buffer 2 full

1

R

Buffer 1 full

0

R

0x58

DMA buffer size

DMA buffer size

31:0

R/W

0x64

DMA destination address - buffer 1, CH1

DMA destination address - buffer 1

31:0

R/W

0x68

DMA destination address - buffer 2, CH1

DMA destination address - buffer 2

31:0

R/W

0x6C

DMA destination address - buffer 1, CH2

DMA destination address - buffer 1

31:0

R/W

0x70

DMA destination address - buffer 2, CH2

DMA destination address - buffer 2

31:0

R/W

Calibration

Offset

Description

Bits

R/W

0x74

Calibration offset value CH1

Reserved

31:16

R

Calibration offset value CH1

15:0

R/W

0x78

Calibration gain value CH1

Reserved

31:16

R

Calibration gain value CH1

15:0

R/W

0x7C

Calibration offset value CH2

Reserved

31:16

R

Calibration offset value CH2

15:0

R/W

0x80

Calibration gain value CH2

Reserved

31:16

R

Calibration gain value CH2

15:0

R/W

0x84

Calibration mode control register

Reserved

31:1

R

Enabling legacy calibration mode.

0

R/W

Note

Legacy calibration mode is enabled for calibration values in versions 1 through 5. This calibration occurs after the frequency filter. Calibration version 6 calibrates values before the frequency filter.


Diagnostics and Lost Samples

Offset

Description

Bits

R/W

0x5C

Number of lost samples CH1 - buffer 1

Counter of lost samples - buffer 1

31:0

R

0x60

Number of lost samples CH1 - buffer 2

Counter of lost samples - buffer 2

31:0

R

0x9C

Number of lost samples CH2 - buffer 1

Counter of lost samples - buffer 1

31:0

R

0xA0

Number of lost samples CH2 - buffer 2

Counter of lost samples - buffer 2

31:0

R

0xA4

Diagnostics - current write pointer CH1

Write pointer

31:0

R

0xA8

Diagnostics - current write pointer CH2

Write pointer

31:0

R

Equalization Filters

Offset

Description

Bits

R/W

0xC0

Filter coefficient AA - CH1

Reserved

31:18

R

AA coefficient

17:0

W

0xC4

Filter coefficient BB - CH1

Reserved

31:24

R

BB coefficient

23:0

W

0xC8

Filter coefficient KK - CH1

Reserved

31:24

R

KK coefficient

23:0

W

0xCC

Filter coefficient PP - CH1

Reserved

31:0

R

PP coefficient

23:0

W

0xD0

Filter coefficient AA - CH2

Reserved

31:18

R

AA coefficient

17:0

W

0xD4

Filter coefficient BB - CH2

Reserved

31:24

R

BB coefficient

23:0

W

0xD8

Filter coefficient KK - CH2

Reserved

31:24

R

KK coefficient

23:0

W

0xDC

Filter coefficient PP - CH2

Reserved

31:0

R

PP coefficient

23:0

W

Board Status

Offset

Description

Bits

R/W

0x100

Board status

Reserved

31:2

R
Board mode:

  • 1 - Slave

  • 0 - Master

1

R

Shows presence of clock on SATA connector.

Bit 0 must be set for this value to be valid.

ADC clock is present, PLL locked

0

R

Counter for timestamps

Offset

Description

Bits

R/W

0x200

Tick counter

Low part of uint64 counter

31:0

R/W

0x204

Tick counter

High part of uint64 counter

31:0

R/W

0x208

Start writing to the first buffer

Low part of uint64 counter

31:0

R/W

0x20C

Start writing to the first buffer

High part of uint64 counter

31:0

R/W

0x210

Start writing to the second buffer

Low part of uint64 counter

31:0

R/W

0x214

Start writing to the second buffer

High part of uint64 counter

31:0

R/W

Note

The counters count in ADC base clocks without taking decimation into account. With a decimation of 1 and a frequency of 125 MHz, the number 8 will be added to each sample.


Back to top


CS[1] - DAC Streaming (0x40100000-0x401FFFFF)

Quick Reference

Offset

Register

R/W

0x0-0x18

DAC channel configuration (mode, amplitude, pointers)

R/W

0x1C-0x24

Event control (status, select, trigger mask)

R/W

0x28-0x44

DMA configuration (control, status, buffers)

R/W

0x48-0x58

Error counters and control

R/W

0x5C-0x64

Digital loopback and bitshift control

R/W

DAC Channel Configuration

Offset

Description

Bits

R/W

0x0

Configuration

Reserved

31:24

R

CH B set output to 0

23

R/W

CH B use 8 bit mode

22

R/W

Reserved

21:20

R/W

CH B trigger selector (don’t change when SM is active): * 1 - Trig immediately * 2 - External trigger positive edge - DIO0_P pin * 3 - External trigger negative edge

19:16

R/W

Reserved

15:8

R

CH A set output to 0

7

R/W

CH A use 8 bit mode

6

R/W

Reserved

5:4

R/W

CH A trigger selector (don’t change when SM is active): * 1 - Trig immediately * 2 - External trigger positive edge - DIO0_P pin * 3 - External trigger negative edge

3:0

R/W

0x4

CH A amplitude scale and offset

out = (data*scale)/0x2000 + offset

Reserved

31:30

R

Amplitude offset

29:16

R/W

Reserved

15:14

R

Amplitude scale. Unsigned

13:0

R/W

0x2000 == multiply by 1

0x8

CH A counter step

Counter step (16 bits for decimals)

31:0

R/W

0xC

CH A buffer current read pointer

Read pointer

31:0

R

0x10

CH B amplitude scale and offset

out = (data*scale)/0x2000 + offset

Reserved

31:30

R

Amplitude offset

29:16

R/W

Reserved

15:14

R

Amplitude scale. Unsigned

13:0

R/W

0x2000 == multiply by 1

0x14

CH B counter step

Counter step (16 bits for decimals)

31:0

R/W

0x18

CH B buffer current read pointer

Read pointer

31:0

R

Event Control

Offset

Description

Bits

R/W

0x1C

Event status register

Reserved

31:4

R

Trigger event

3

R/W

Stop event

2

R/W

Start event

1

R/W

Reset event

0

R/W

0x20

Event select register

Reserved

31:5

R

Logic analyser event

4

W

Scope CHB event

3

W

Scope CHA event

2

W

Signal generator CHB event

1

W

Signal generator CHA event

0

W

0x24

Trigger mask

Reserved

31:5

R

Logic analyser trigger

4

W

Scope CH B trigger

3

W

Scope CH A trigger

2

W

Signal generator CH B trigger

1

W

Signal generator CH A trigger

0

W

DMA Configuration

Offset

Description

Bits

R/W

0x28

DMA control register

Reserved

31:14

R

Buffer 2 ready CHB

15

W

Buffer 1 ready CHB

14

W

Streaming DMA mode CHB

13

W

Normal DMA mode CHB

12

W

Reserved

11:10

R

Reset buffers and flags CHB

9

W

Start DMA CHB

8

W

Buffer 2 ready CHA

7

W

Buffer 1 ready CHA

6

W

Streaming DMA mode CHA

5

W

Normal DMA mode CHA

4

W

Reserved

3:2

R

Reset buffers and flags CHA

1

W

Start DMA CHA

0

W

0x2C

DMA status register

Reserved

31:23

R

Sending DMA REQ buffer 2 state

22

R

Sending DMA REQ buffer 1 state

21

R

Reset state

20

R

End state buffer 2

19

R

Read state buffer 2

18

R

End state buffer 1

17

R

Read state buffer 1

16

R

Reserved

15:7

R

Sending DMA REQ buffer 2 state

6

R

Sending DMA REQ buffer 1 state

5

R

Reset state

4

R

End state buffer 2

3

R

Read state buffer 2

2

R

End state buffer 1

1

R

Read state buffer 1

0

R

0x34

DMA buffer size

DMA buffer size

31:0

R/W

0x38

DMA buffer 1 address CH A

DMA buffer address

31:0

R/W

0x3C

DMA buffer 2 address CH A

DMA buffer address

31:0

R/W

0x40

DMA buffer 1 address CH B

DMA buffer address

31:0

R/W

0x44

DMA buffer 2 address CH B

DMA buffer address

31:0

R/W

Error Counters

Offset

Description

Bits

R/W

0x48

Error counter expected step CHA

Reserved

31:16

R

Counter step (due to decimation)

15:0

W

0x4C

Error counter expected step CHB

Reserved

31:16

R

Counter step (due to decimation)

15:0

W

0x50

Reset error counters

Reserved

31:1

R

Reset error counters

0

W

0x54

Error counter CHA

Number of errors

31:0

R

0x58

Error counter CHB

Number of errors

31:0

R

Digital Loopback and Bitshift

Offset

Description

Bits

R/W

0x5C

Digital loopback

Reserved

31:8

R

DAC CH2

7:5

R

Loopback DAC CH2 - output raw data

4

W

DAC CH1

3:1

R

Loopback DAC CH1 - output raw data

0

W

0x60

Bitshift right CHA

Shift raw data from RAM right

31:5

R

Shift in number of bits

4:0

R/W

0x64

Bitshift right CHB

Shift raw data from RAM right

31:5

R

Shift in number of bits

4:0

R/W

Back to top


CS[2] - GPIO Streaming (0x40200000-0x402FFFFF)

The GPIO Streaming module provides bidirectional GPIO data streaming with RLE encoding support, triggering, and DMA control.

Quick Reference

Offset

Register

R/W

0x0-0x4

GPIO status and acquire mode

R/W

0x10-0x4C

Trigger control and status

R/W

0x50-0x60

Data processing control (decimation, RLE, polarity)

R/W

0x70-0x74

GPIO direction control (P/N)

R/W

0x80-0x88

Event control (select, trigger mask, status)

R/W

0x8C-0x98

DMA configuration (status, buffers, missed counters)

R/W

0xB8-0xC0

GPIO output control (pointers, step)

R/W

RLE Output Encoding

RLE output encoding:

The written number of samples equals (desired number - 1), max 0xFF (8 bits available). Not less than 1 - limited to one change per 2 clock cycles. A 32-bit chunk of data is structured like this:

  • [ 7: 0] RLE decode number for all bits

  • [15: 0] Reserved

  • [23:16] GPIO_x_N bits

  • [31:24] GPIO_x_P bits


Status and Configuration

Offset

Description

Bits

R/W

0x0

GPIO Status reg

Reserved

31:4

R

Acquire stopped

3

R

Acquire start

2

R

Trigger received

1

R

Reserved

0

0x4

Acquire mode

Reserved

31:2

R

Automatic mode

1

R/W

Continous mode

0

R/W

Trigger Control and Status

Offset

Description

Bits

R/W

0x10

Number of pre-trigger samples

Number of samples

31:0

R/W

0x14

Number of post-trigger samples

Number of samples

31:0

R/W

0x18

Current pre-trigger samples

Number of samples

31:0

R/W

0x1C

Current post-trigger samples

Number of samples

31:0

R/W

0x20

Timestamp of acquire - low bits

Timestamp[31:0]

31:0

R

0x24

Timestamp of acquire - high bits

Timestamp[63:32]

31:0

R

0x28

Timestamp of trigger - low bits

Timestamp[31:0]

31:0

R

0x2C

Timestamp of trigger - high bits

Timestamp[63:32]

31:0

R

0x30

Timestamp of stop - low bits

Timestamp[31:0]

31:0

R

0x34

Timestamp of stop - high bits

Timestamp[63:32]

31:0

R

0x40

Trigger - comparator mask

Reserved

31:8

R

Comparator mask

7:0

R/W

0x44

Trigger - comparator value

Reserved

31:8

R

Comparator value

7:0

R/W

0x48

Trigger - positive edge

Reserved

31:8

R

Negative edge

7:0

R/W

0x4C

Trigger - negative edge

Reserved

31:8

R

Negative edge

7:0

R/W

Data Processing Control

Offset

Description

Bits

R/W

0x50

Decimation factor

Decimation factor

31:0

R/W

0x54

RLE enable

Reserved

31:1

R

RLE enable

0

R/W

0x58

Current counter

Counter

31:0

R

0x5C

Last packet

Counter

31:0

R

0x60

Input polarity

Reserved

31:8

R

Input polarity

7:0

R/W

GPIO Configuration

offset

description

bits

R/W

0x70

GPIO direction - p

Reserved

31:8

R

GPIO direction

7:0

R/W

0x74

GPIO direction - n

Reserved

31:8

R

GPIO direction

7:0

R/W

0xB8

GPIO IN - write pointer

Write pointer

31:0

R/W

0xBC

GPIO OUT - read pointer

Read pointer

31:0

R/W

0xC0

GPIO OUT - step of read pointer

Step

31:0

R/W

Event Control

offset

description

bits

R/W

0x80

Event select register

Reserved

31:5

R

Logic analyser event

4

W

Scope CHB event

3

W

Scope CHA event

2

W

Signal generator CHB event

1

W

Signal generator CHA event

0

W

0x84

Trigger mask

Reserved

31:6

R

External trigger

5

W

Logic analyser trigger

4

W

Scope CH B trigger

3

W

Scope CH A trigger

2

W

Signal generator CH B trigger

1

W

Signal generator CH A trigger

0

W

0x88

Event status register

Reserved

31:4

R

Trigger event

3

R/W

Stop event

2

R/W

Start event

1

R/W

Reset event

0

R/W

DMA Configuration

offset

description

bits

R/W

0x8C

DMA control register - IN

Reserved

31:10

R

Streaming DMA mode

9

W

Normal DMA mode

8

W

Reserved

7:5

R

Reset buffers and flags

4

W

Buffer 2 acknowledge

3

W

Buffer 1 acknowledge

2

W

Interrupt acknowledge

1

W

Start DMA

0

W

0x90

DMA control register - OUT

Reserved

31:8

R

Buffer 2 ready OUT

7

W

Buffer 1 ready OUT

6

W

Streaming DMA mode OUT

5

W

Normal DMA mode OUT

4

W

Reserved

3:2

R

Reset buffers and flags OUT

1

W

Start DMA OUT

0

W

0x94

DMA status register IN

Reserved

31:4

R

Buffer 2 overflow

3

R

Buffer 1 overflow

2

R

Buffer 2 full

1

R

Buffer 1 full

0

R

0x98

DMA status register OUT

Reserved

31:5

R

Reset state

4

R

Read state buffer 2

3

R

End state buffer 2

2

R

Read state buffer 1

1

R

End state buffer 1

0

R

0x9C

DMA buffer size

DMA buffer size

31:0

R/W

0xA0

DMA buffer 1 address IN

DMA buffer address

31:0

R/W

0xA4

DMA buffer 1 address OUT

DMA buffer address

31:0

R/W

0xA8

DMA buffer 2 address IN

DMA buffer address

31:0

R/W

0xAC

DMA buffer 2 address OUT

DMA buffer address

31:0

R/W

0xB0

Buffer 1 missed sample counter IN

Number of missed samples

31:0

R/W

0xB4

Buffer 2 missed sample counter IN

Number of missed samples

31:0

R/W

Back to top