3.1.3.3. External ADC clockΒΆ

ADC clock can be provided by:
  • On board 125MHz XO (default)
  • From external source / through extension connector E2 (R25,R26 should be moved to location R23,R24)
  • Directly from FPGA (R25,R26 should be moved to location R27,R28)

Schematic:

../../_images/External_clk.png

Top side:

../../_images/External_clock_top.png

Bottom side:

../../_images/External_clock_bottom.png