3.1.1.3. STEMlab 125-14 external clock

This STEMlab version is standard STEMlab 125-14 modified in such a way that the ADC and DAC clock can be provided from an external source clock. External clock should be connected to Ext ADC CLK- and + pins. External clock signal levels should be LVDS in the range from 1MHz to 125MHz according to ADC spec.

../../../_images/Extension_connector.png

3.1.1.3.1. Technical specifications

3.1.1.3.2. Schematics

Note

Red Pitaya board HW FULL schematics are not available. Red Pitaya has an open source code but not an open hardware schematics. Nonetheless, DEVELOPMENT schematics are available. This schematic will give you information about HW configuration, FPGA pin connection and similar.

3.1.1.3.3. Mechanical specifications

3.1.1.3.4. ADC specifications

3.1.1.3.5. RP clock wiring

For all other specifications please refer to standard STEMlab 125-14 specs.