3.1.1.2. STEMlab 125-14¶
3.1.1.2.1. Technical specifications¶
Basic |
|
---|---|
Processor |
DUAL CORE ARM CORTEX A9 |
FPGA |
FPGA Xilinx Zynq 7010 SOC |
RAM |
512 MB (4 Gb) |
System memory |
Micro SD up to 32 GB |
Console connection |
Micro USB |
Power connector |
Micro USB |
Power consumption |
5 V, 2 A max |
Connectivity |
|
---|---|
Ethernet |
1 Gbit |
USB |
USB 2.0 |
WIFI |
requires WIFI dongle |
RF inputs |
|
---|---|
RF input channels |
2 |
Sample rate |
125 MS/s |
ADC resolution |
14 bit |
Input impedance |
1 MOhm / 10 pF |
Full scale voltage range |
±1 V (LV) and ±20 V (HV) |
Input coupling |
DC |
Absolute max. Input voltage range |
30 V |
Input ESD protection |
Yes |
Overload protection |
Protection diodes |
Bandwidth |
DC - 60 MHz |
RF outputs |
|
---|---|
RF output channels |
2 |
Sample rate |
125 MS/s |
DAC resolution |
14 bit |
Load impedance |
50 Ohm |
Voltage range |
±1 V |
Short circut protection |
Yes |
Connector type |
SMA |
Output slew rate |
2 V / 10 ns |
Bandwidth |
DC - 50 MHz |
Extension connector |
|
---|---|
Digital IOs |
16 |
Analog inputs |
4 |
Analog inputs voltage range |
0-3.5 V |
Sample rate |
100 kS/s |
Resolution |
12 bit |
Analog outputs |
4 |
Analog outputs voltage range |
0-1.8 V |
Communication interfaces |
I2C, SPI, UART |
Available voltages |
+5 V, +3.3 V, -4 V |
external ADC clock |
yes |
Synchronisation |
|
---|---|
Trigger input |
Through extension connector |
Daisy chain connection |
Over SATA connection (up to 500 Mbps) |
Ref. clock input |
N/A |
Note
For more information, please refer to the Product comparison table.
3.1.1.2.2. Schematics¶
Note
FULL HW schematics for the Red Pitaya board are not available. Red Pitaya has open source code but not open hardware schematics. Nonetheless, DEVELOPMENT schematics are available. This schematic will give you information about HW configuration, FPGA pin connections, and similar.
3.1.1.2.3. Mechanical specifications¶
3.1.1.2.4. Components¶
Note
STEMlab 125-14 Low Noise and STEMlab 125-14 4-Input feature Zynq 7020 instead of Zynq 7010.
3.1.1.2.5. Fast analog IO¶
- 3.1.1.2.5.1. Analog inputs
- 3.1.1.2.5.1.1. General Specifications
- 3.1.1.2.5.1.1.1. Jumpers
- 3.1.1.2.5.1.1.2. Jumper orientation
- 3.1.1.2.5.1.1.3. Input stage schematics
- 3.1.1.2.5.1.1.4. Coupling
- 3.1.1.2.5.1.1.5. Bandwidth
- 3.1.1.2.5.1.1.6. Input noise
- 3.1.1.2.5.1.1.7. Input channel isolation
- 3.1.1.2.5.1.1.8. Harmonics
- 3.1.1.2.5.1.1.9. Spurious frequency components
- 3.1.1.2.5.1.1.10. Reference signals
- 3.1.1.2.5.1.1.11. DC offset error
- 3.1.1.2.5.1.1.12. Gain error
- 3.1.1.2.5.1.2. Analog inputs calibration
- 3.1.1.2.5.1.1. General Specifications
- 3.1.1.2.5.2. Analog outputs
3.1.1.2.6. Extension¶
3.1.1.2.7. External ADC clock¶
The ADC clock can be provided by:
On board 125 MHz XO (default)
From an external source/through extension connector E2 (R25, R26 should be moved to location R23, R24)
Directly from the FPGA (R25, R26 should be relocated to R27, R28)

Schematic¶
Warning
We do not advise altering the board because users have reported problems after doing so. Every board made has undergone rigorous testing, which cannot be claimed for modified boards. Any non-Red Pitaya hardware modification will void the warranty, and we cannot guarantee support for modified boards.

Top side¶

Bottom side¶
3.1.1.2.8. Certificates¶
Besides the functional testing, Red Pitaya passed the safety and electromagnetic compatibility (EMC) tests at an external testing and certification institute.
3.1.1.2.9. Cooling options¶
For additional cooling, we recommend a 30 mm or 25 mm fan. You can utilise the power connector on the board to power the fan, but please note that it supplies only 5 V. The power connector is located between the micro-SD socket and the host USB connector.
Note
The power connector is a standard 2-pin 0.1” connector. Supplies only 5 V.