3.1.1.9. SDRlab 122-16 external clock

This SDRlab version is standard SDRlab 122-16 modified in such a way that the ADC and DAC clock can be provided from an external source clock. External clock should be connected to Ext ADC CLK- and + pins. External clock signal levels should be LVDS in the range from 1 MHz to 122.8 MHz according to ADC spec.

Note

The OS will not boot without providing an external clock.

3.1.1.9.1. Technical specifications

Basic
Processor	DUAL CORE ARM CORTEX A9
FPGA	FPGA Xilinx Zynq 7020 SOC
RAM	512 MB (4 Gb)
System memory	Micro SD up to 32 GB
Console connection	Micro USB
Power connector	Micro USB
Power consumption	5 V, 2 A max

Connectivity
Ethernet	1 Gbit
USB	USB 2.0
WIFI	requires WIFI dongle

RF inputs
RF input channels	2
Sample rate	122.88 MS/s
ADC resolution	16 bit
Input impedance	50 Ohm
Full scale voltage range	0.5 Vpp/-2 dBm
Input coupling	AC
Absolute max. Input voltage range	DC max 50 V (AC-coupled) 1 Vpp for RF
Input ESD protection	Yes
Overload protection	DC voltage protection
Bandwidth	300 kHz - 550 MHz (undersampling)

RF outputs
RF output channels	2
Sample rate	122.88 MS/s
DAC resolution	14 bit
Load impedance	50 Ohm
Voltage range	0.5 Vpp/ -2 dBm (50 Ohm load)
Short circut protection	N/A, RF transformer & AC-coupled
Connector type	SMA
Output slew rate	N/A
Bandwidth	300 kHz - 60 MHz

Extension connector
Digital IOs	16
Analog inputs	4
Analog inputs voltage range	0-3.5 V
Sample rate	100 kS/s
Resolution	12 bit
Analog outputs	4
Analog outputs voltage range	0-1.8 V
Communication interfaces	I2C, SPI, UART
Available voltages	+5 V, +3.3 V, -4 V
external ADC clock	yes

Synchronisation
Trigger input	Through extension connector
Daisy chain connection	Over SATA connection (up to 500 Mbps)
Ref. clock input	N/A

Note

For more information, please refer to the Product comparison table.

3.1.1.9.2. Schematics

• STEM122-16SDR_V1r1_Series1.PDF

Note

Red Pitaya board HW FULL schematics are not available. Red Pitaya has an open source code but not an open hardware schematics. Nonetheless, DEVELOPMENT schematics are available. This schematic will give you information about HW configuration, FPGA pin connection and similar.

3.1.1.9.3. Mechanical specifications

• STEM122-16SDR_V1r1_3Dpdf.zip

• STEM122-16SDR_V1r1_3Dstep.zip

3.1.1.9.4. ADC specifications

• Data sheets

3.1.1.9.5. RP clock wiring

• External ADC clock

For all other specifications please refer to standard SDRlab 122-16 specs.